Early stage design often uses some very simple tests to check for it breing brain dead - test reset et and possible other simple functions. During this time, constrained random testbench built. You dont want to be debugging very simple iussues with constrained random.
Thank you Brian. The course gave a good overview of nowadays design verification. The course really helped to reactivate my knowledge of design verfication, while I'm currently busy at the algorithmic layer (research).
It seems that through register layer virtual seq & scoreboard interacts with uvm_agent? Shouldn't this interction through port & export instead of register layar. Im unable to understand what register layar is? Is it a sort of interface?
It would be the virtual sequencer that decided to initiate a DMA. It woulod probably have been monitor the bus to know when it was free or possible. Or it could have asked the arbitrator when it could successfully do the operation. Depends if the arbitrator is in the design.
I agree verification plan is WHAT not How ... but are there elements in the plan you want to see or would demand to see that make your job doable or easier as it relates to transitioning into the detailed verification design where a consideration of Systemverilog / UVM is taken into account ...
No - UVM and the earlier versions only came about in the past 5 or 6 yyears. Magma was more into back end and custom design and analog stuff. They diid very litttleie front end, which is where functional verification sits.
It would be great to present a more practical course. One that will present the steps of FPGA design with a real example that could be replicated by the attendees. I don't mean all the details but including some useful tips coming from design experience.
I read more or less about OVM and UVM, but for what use if there is no tool (free or with size limitation) that I can use to exercise it. Is like learning programming without computer.
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YEs - I have started having hotels and restaurants offer me a senior discount. Why? I still make the same impression in the bed and eat as much food! It seems strange, but I am cheap, so I use whatever discounts I can get.
@Kentj - take a look at this book as an alternative to the manual: http://www.eetimes.com/electronics-blogs/eda-designline-blog/4410232/Book--Analog-Design-and-Simulation-using-OrCAD-Capture-and-PSpice
I have a son-in-law that fixes IE after its release. He tries to make it work before hand but they seem to frown on that. Two different departments and they don't like intercommunication between departments.
I just downloaded OrCAD Lite (Complete). How do you view the tutorial? You seem to need to log in. To log in you need an account. To get an account you need a license. There is no license with the Lite version.
Pinging reminds me of the early days with a phone modem. The phone cable went under Puget Sound and when a submarine would go by it would ping the cable with its sonar and send a lot of garbage across. It was especially bad when downloading a large program at those slow baud rates. It would ping near the end of an hour long download and you would have to start over.
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From design feasibility, to development, to production, having the right information to make good decisions can ultimately keep a product from failing validation. The key is highly focused information that doesn’t come from conventional, statistics-based tests but from accelerated stress testing.
There’s a good chance that a few of the things mentioned here won't fully come to fruition in 2015 but rather much later down the line. However, as Malcolm X once said, "The future belongs to those who prepare for it today."
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