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It's another way to day 5 for FUNCTIONAL VERIFICATION...excellent presentation sir brian, much appreciated and thanks once again...

i am now about to close and go with the day 5 lecture...for the conclusion of the lecture...

once agan, thanks to all...

eventhough i missed this live lecture, i can go straight with the lecture from day 1 to day 5 and that's GREAT...

GREAT! another lecture to learn & reminders about programming...interesting topic sir brian, appreciated much...i am now on slide 21...

i am now on slide 16 of the topic...

i think i need to go back to university to continue INFORMATION MANAGEMENT in particular with programming...it's GREAT!

i am now on slide 6...

i am now about to start the day 4 lecture...

i am now downloading the educational material for this lecture and for future reference as well...

good morning once again sir brian, i am here to continue your lecture...

Very informative lecture

Iron

Great to have access to the recorded sessions!

Iron

Missed the live lecture

Iron

Taking the class offline

Iron

hello all from chilly Edmonton, Alberta.

Iron

Thanks Brian for this great lecture.

Iron

Be better late than never

Thanks as always Brian.

Iron

would like to start using Verilog

Iron

we use a home grown test set

Iron

Thank you for providing more insight

Iron

Internet problems prompted later acces

Iron

Excellent.  Thank you so much!

Iron

Thanks for the hints. Definitely of use for me.

Iron

Well, time for me to go. See everyone tomorrow.

This may be very necessary for interfaces where the data is not 100% aligned with the clock edge.

so the point of sampling may not be the posedge.. o/p assignement will be after the time units specified in #n, which may not be aligned to the posedge of clk, right?

Iron

Good chapter in the book ESL models and their application on the use of CatapultC.

Depends on the way in which the input description is written. You must have knowledge of hardware structures to properly drive the tools.

Result quality is often as good as or in ssome cases better than hand coded.

Also allows for architectural exploration.

HLS is mature and provides good productivity improvement. (do this in pieces)

Grrr. Another HLS response eaten!!!

 

HLS tools are mature - much higher productivity and allow for architectural exploration.

The clock edge is a trigger but necessarily the point of sampling.

But the delay is on the output assignment.

Grrrr. Long post on HLS just got lost!

 

But you were using clocking block in slide 12,,@posedge clk will always sample or drive on the posedge of clock. If i write #1 then the o/p which is driven may not be aligned to posedge of clk?

Iron

OK, good presentation, I might add a slide to explain the 'caveats' section a little more, as you did verbally in the presentation and explanations -- looking forward to the next class

VHDL to SV still more problematic but probably 95% of the capability now there. Verilog to SV is 99.5%

Alright, thank you Brian.

But how good are the results of these tools. I ofter heard from people experimenting with autogenerators/translators, that the effort correcting the results of them was higher than the manual porting. At which level are these statements correct? And how matured are those tools nowadays?

Iron

or it could be 1 milli second

Did your post at 2:47:49PM (no post reference numbers here) anticipate / address the portability from existing VHDL or VeriLog to SystemVerilog?

No - one time unit could be 1 pico second

Isn't they same - 1 time unit & one clock

Iron

There were a few constructs depracated, but that was because they were very rarely used. SV should accept all legal Verilog except for those. Sorry I am not of the list of features that were depracted.

Ah slide 12. #1 is 1 time unit #1step is one clock

What are compatability / portability issues?  Say I have a design from 2006 that a customer wants to use as a baseline and add features and functions to today in SystemVerilog, with the code as a deliverable?

 

There are none that go from abstract SV to RTL constructs.

input  #1step data

Is there a difference in #1 and #1step?

Iron

There are several high-level synthesis tools that will take you from C,C+ ,SystemC to Verilog/VHDL/SV

There was a question about SystemC having a hole. Not sure I understood the question.

I was reffering to the "design gap" between a systemC model and the porting towards HDL. If I understood the 'caveats' slide correctly, I'd assume that there exists a similar gap regarding the workflow inbetween the single parts of the systemverilog language as well. Or ist more complete (OOP -> RTL)?

Iron

what unique keyword implies?

Iron

UVM is built on top of SV. SV provides the class language, UVM defines the base classes and commmonly used functionality.

Import all of the variables with the same names.

constraint ssolvers have improved by they can still consume a lot of time.

what is the difference between UVM and systemverilog standard class based verification? Can I use these methods to verify a small design ? I need to get started with systemverilog and looking forward to know how to get handson ?

Iron

When you used import pkg :: *, what's the meaning of ::* ?

Iron

Thanks @tariq786 and @brian_bailey

Iron

Brian:

Has constraint compilation improved with the use of SV? I remember with Specman (e) that sometimes the tool would try to resolve your random constraints for 30min, only to let you know at the end that you had a deadlock...

Iron

Seems my last comment got lost. I said that if assertions are put in interfaces they are easier to reuse and turn on and off by the simulator.

 

Wohoo, messages get lost again ;)

Iron

if the condition fails i can print error in the else statement as well

Iron

An assert creates an error when triggered. YOu could use a print and write the assertion in VErilog. The new SVA language is way more powerful though.

Why do we use assert statements instead of if-else?

Iron

Thanks tariq. Totally correct. The only caveat I would make is that it is no lnger possible to see them as separate stages. Physicl synthesis has brough a bunch of them together.

 

@bob loy

RTL -> synthesis ->  gate-level verilog -> Place & Route -> layout level verilog -> masks

Iron

RTL -> synthesis ->  gate-level verilog -> Place & Route -> layout level verilog -> masks

Iron

The big difference is the way it does checking and the default condition. Impllied registers used to be created for cases that were not covered and that was nnot always wanted."comb" says there should be no register.

@Alka

 

always @

can infer latch logic if you are not careful with writing verilog. Always_comb makes sure that combinational  logic is inferred

Iron

Dont learn SuperLog. It is just part of history now.

 

Thank you. See you tomorrow

Iron

Sometimes I fogot to press [post]

Iron

What is the "distance" between the RTL part of SystemVerilog (or SystemC for that matter) and final IC mask sets?

Iron

Test - my question didn't seem to post - test

Iron

There was a question about SystemC having a hole. Not sure I understood the question.

Very useful lecture. Thanks Brian.

 

 

Iron

Thank you for an informative lecture

Blogger

@ADiewi - seems that is what the 'caveat'  is about ...

Thank you Brain for another informative presentation!

Iron

Thank you Brian, that was a very clear overview of the language and its concepts.

Iron

Messed something up here

 

Thanks.  SystemVerilog looks very interesting. 

Iron

What's the difference in always_comb & always except that always_comb is used for combinational logic?

Iron

Thanks Brian for the great presentation

Iron

Thanks Brian and all.

Iron

Excellent presentation, thanks alot

Iron

Thank you, Brian. Really enjoying this series of lectures!

Iron

Thank you Brian.

I am very interested in learning more about Superlog.

Iron

Thanks Brian, anothe great presentation!!

Iron

Excellent lecture, thank you.

Iron

Excellent behind-the-scenes details for this high level introduction. Thanks!

Iron

now can see what you mean by 'CAVEATS' .. the slide itself isnt clear that way ... good explanation

I've lost audio connection completely

Iron

It seems to me that SystemVerilog has a similar gap here like SystemC and VHDL. Am I completely off the road with this assumtion?

Iron

I haven't started using SystemVerilog yet.

Iron

used verilog in the past for design and testbench

Iron

My company has standardized on VHDL -- it's hard to turn a very large ship that's going very fast (in terms of existing IP, internal scripts/tools, personnel training)

... it's unlikely we'll switch in the forseeable future.

Blogger

I am using Verilog, but not the features described here.

Iron

I'm using it for design

Iron

not using verilog at this point.

Iron

 

I had no problem on the previous 3 days. I haven't changed anything...so what happened ?

Iron

finally I can hear

Iron

 

It took 7 or 8 refreshes... and I do use Firefox

Iron

Thanks drw36. After refreshing the browser, the audio finally works.

Iron

Had to go to a broswer that usually doesn't work for these streams; now it works.

Iron

Please refresh your browswer and hit the play button again. Try twice if necessary. Also, please use Firefox or Chrome.

missed first few minutes.....

 

Iron

Now, My audio is on and clear.

Iron

Had to refresh browser window several times to get audio working today.

Iron

Hello from Milwaukee!

Iron

Audio just won't start today...

Iron

Audio problems already.  Had to F5.

Iron

I cann't use my Audio.

Iron

Hello From sunny Toronto.

Iron

Hi all - Audio is live!

I don't know SystemVerilog; I thought SystemC was the coming thing, but from yesterday's discussion I guess I was wrong...

Iron

YEs - SystemVerilog skills in demand

ModelSim supports SystemVerilog.  Many jobs out there for SystemVerilog!

Iron

Hello from Placentia CA.

Iron

Greetings from Florida, or possibly Portland. Been cloudy/rainy here for > 24 hrs; not our usual afternoon popup T-storm mode.

Iron

Good morning from Newport Beach, CA

I've started a testbench in SystemVerilog, which includes tlm_fifos, the driver, DUT, responder, tester, printer and the top level module(fork/join_none) by following a book by Ray Salemi

Iron

who sat on the committees for the new standards - anyone from Mil/Aero, Automotive, Medical communities?  ADA may have stricter type standards, but C still dominates the industry for familiarity ...

 

Good Morning from CA

Iron

@Digital Angel - in a way yes. They did not add any new capabilities, just a cleaner syntax.

I have used Verilog but not System Verilog, new to it.

Iron

Extra marks to anyone who has the answer...

Are "C-like control constructs and data types" a caveat?

 

Good afternoon, never used SystemVerilog.

Iron

Ah Superlog. Some of my old buddies were at that company - the original Hilo team. Phil Moorbey then left the team and created a new version that was called AidSim. Anyone want to guess what it was renamed when the aids epidemic hit the headlines?

I've known about it for a fairly long time... but I have never actually used it.

I used Zero-In assertions at Nortel before Superlog and SV were born.

Iron

Hey Brian, I am briefly familiar with some of the syntax, but havent really used it to a great extent!! 

 

Iron

I don't know anything about it.

 

Iron

Lets start off with a question even before we get started: How many of you know about SystemVerilog and perhaps have even used parts of it?

Good morning, afternoon or evening... It's afternoon here in Ottawa

Iron

I need another coffee before I get started.

 

@salmanisheikh

 

How are you?

Iron

Be sure to follow @designnews and @DigikeyCEC on Twitter for the latest class information. We encourage you to Tweet about today's class using the hashtag #CEC.

Blogger

Please join our Digi-Key Continuing Education Center Linkedin Group at http://linkd.in/yoNGeY.

Blogger

The streaming audio player will appear on this web page when the show starts at 2 p.m. ET today. Note, however, that some companies block live audio streams. If you don't hear any audio when the show starts, try refreshing your browser.

Blogger

Be sure to click "Today's Slide Deck" under Special Educational Materials above right to download the Powerpoint for today's session.

Blogger

Hello from Chicago, sunny and 54F!

Blogger

Hello from rainy Atlanta

 

Iron

Good Morning everyone.  Awaiting another excellent lecture.

I am learninh SystemVerilog.

Iron

Good morning from Vancouver.

Iron

It is wet and cool here today in Huntsville, AL, in the 80's this week end.

Iron

Good Afternoon from the currently SUNNY Six State to enter the Union.LOL

Iron

Good afternoon from sunny Brick, NJ

Iron

Hello from Sunny SE Lake Simcoe Ontario Canada

Iron

The Early Birds are out!

Iron

Good morning from Edmonton, AB

Iron

Good morning from North Pole, AK

Iron

Good morning from Scottsdale, AZ

Iron

@brian_bailey:  I'm just here for the chat this early.  Sometimes there are some good questions asked.  Other times we talk about coffee.  I don't have an espresso machine.  And I'm happy they took out the sugar alcohol from the sugar free coffee flavors.  Sugar alcohol is still sugar and I'm on insulin.

Iron

Good morning everyone that it's morning for, from Richmond, TX

Iron

Good morning from Portland Oregon

Iron

Good Morning, everyone

Iron

Good morning from Mobile, AL

look ahead ... need to think on it before bed

 

What are you folks doing logged in already? I won';t give you a better grade :)



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