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excellent ideas to ponder

Iron

bye all and see you all in the next class schedule on June 10 for a live lecture...

I do thank DIGI-KEY and DESIGN NEWS once again for giving this kind of continuing education and exploring our mind into a new world with all the topics for us to know...

excellent presentation sir brian, i appreciates alot...

i will go for the next lecture for day 4....thanks once again...

although i am not in electronics industry, but i do understand a little bit. However, as a part of continuing education, i am enjoying listening the lectures and got an ideas..it looks like I am in University class room to learn about the subject...

I do appreciates the lecture and very interesting to learn more all about especially i am now preparing for instrumentation and control certification examination...

i am now on slide 13 of this topic...thanks to sir brian...

i am now on slide 9 about functional coverage...

I am now in slide 7 for constrained random...

i am now at slide 2 of day 3 lecture of functional verification...

i am now downloading the slides of your lecture sir brian just to follow the discussion and for reference as well...thanks.

good morning sir brian!

i am her again to continue your lecture...

Very informative lecture

Iron

Great to have access to the recorded sessions!

Iron

Missed the live lecture

Iron

Taking the class offline

Iron

most test pattern generation is done manually until I want to hammer on a troublesome condition with an automated sequence.

Iron

I tend to shake out bugs and ill-formed design by random stimuli that does not normally happen.

Some of the responses are really "interesting".

Iron

still in the world of walking through the code on paper to work through all the execution paths.

Iron

hello all from chilly Edmonton, Alberta. It stopped snowing for a while.

Iron

We are going to be using more formal code coverage testing

closing in on getting caught up

Good presentation, answered a lot of questions.  Also the comment/Blog dialogue was useful in bring up ideas and answering questions - good job all ...


Verification methodologies at the FUNCTIONAL level should include both functional coverage and path coverage.  The hybrid approach along with segment and unit level testing helps the verification process.  Constrained Random is a sort of hybrid approach at the stimulus - response (functional) level but may or may not take path testing into account which should not be overlooked.

Finally caught up to the class and took a look-ahead.  This is a good overview of functional verification at a very high level.  Implementation in the mission critical domains such as Military, Medical or Automotive industries have processes and mechanisms that can provide insight and examples into the process. 

Jack Ganssle's class in the Digi-Key CEC (and writings online) on approach/method, concepts, philosophy for design, test and debug in general can also help in getting a mindset of good practices.

Florida back. I'm only 2 hours behind!

Iron

@digital angel - That is normally the role of the verification plan and is mostly an informal process today. Many designers say going from that to the coverage model is one of the most difficult aspects of verification.

good stuff, have a little catch up to do, thanks for the great slides and presentation thus far ...

 

Well, I do have to go. See you all tomorow when we talk about SystemVerilog

 

Brian, for example a project engineer, with say three designers under him/her, wants to insure technical/functional and contract coverage of a design, is there an intermediate approach in going from spec to verification that can be handed off to a designer?

@pbrodeur. Thanks. I forgot I had put it theree. That was slavaged from a site that no longer exists. The book does go into the subject in a lot more depth. When I first came up with the concept it even took a while before verification experts accepted it, but eventually they do. It is not widely talked about because the EDA industry has no tools for positive verification.

Sorry if I missed any of your questions. Tough to keep up at times.

I found that blog by brian on positive/negative verification:

http://www.brianbailey.us/blog/?p=344

Iron

@digital angel. Not sure what you are asking? RTL very bad at defining assertions. Properties can be defined using several langauges, most of whcih are based on declarative language concepts.

 

@brian. Sent you an email. Please reply at your earliest convenience.


Thanks again

Iron

@asicsoc - Most people today would use constrained random as it will allow you to spend your time definning how tests should be created rather than aactual;ly creating the tests. The actual tests come for free. Constrained randdom also very useful for finding the things you never thought to test. HOwever, constrained random will fail to fill some coverage holes and for those revert to directed testing using the same predictors/checkers

@alka - yes, but we have to make sure that when IP blocks are connected together that they actually perform the necessary function. Think of this in board terms. Even if the components all work, does that imply that your design works? Have to do high level tests as well to prove the device does something useful.

Given a spec for a sub module in SOC, what is the best way to verify functionality? 

Iron

Also, never used constrained tests

Iron

In regard to going from a spec to a set of assertions, care to comment on RTL or other pseudo language or programming modeling concepts or tools?

 

have never used constrained patterns

Iron

CDC is also a very specialized form of formal verification.

Did you mean when we say verifiaction it implies negative verification..as our main goal is to make sure bugs do not exist, right?

Iron

@tariq - agreed. In formal everythingg is defined formally rather than procedurally.

Going from a spec to a set of assertions is difficult and takes some experience. There is a library (Open Verification Library) that has some typical components and assertions pre defined. It may be good to look at those and see the kiinndds of things and ways that assertions can be defined. High-levell asertions caan be very difficuult to write.

 

@Brian

I think its worth mentioning that formal scoreboard is different from simulation scoreboard. Formal scoreboard is more about packet integrity. For example Jaspergold tool from Jasper design automation use formal scoreboard to prove data integrity across clock domain crossing (CDC)

On the other hand, simulation scoreboard keeps track of the tests like which ones have been done and which remain. At the end simulation scoreboard should be empty. Its more like test tracker.

 

Please share your thoughts

Iron

@Brian

OK thanks, I will search the web for some explanations. Do you have links you can recommend?

Iron

If the response checker has a built in predictor model, then that is OK. It would be better fopr the predictor to have been written seperately because it can then be reused.

Janics books are all about constrained random and do not talk about directed testing, so do not talk about positive verification directly.

Pos/Neg is a difficult concept to explain in a couple of m inutes, and in part verification methodologies in use today almost discourage the usage of positive verification. Directed test much better in this regard.

I've generally seen checker in my IP verification but no scoreboard. Is it ok to have just response checker?

Iron

What is the best way to write Assertions from SOC spec?

Iron

Janic did not cover the concept. It was first covered in ESL Design and Verification I think (by me).

IWhile SystemC can be used at RTL - I highly doscourage its usage there. It is slow compared to VErilog/VHDL simulators. But at the system-level it is good and the fact that it can "contain" C code, which may already exist, makes it very useful. SystemVErilog can also contain C, but not quite as readily.

@Brian

I find the difference between positive and negative verification rather vague. I don't remember those concepts being addressed in the original book from Janick (circa 2000). Does he cover this subject in the System Verilog book?

Iron

I have successfully used SystemC for behavioral modeling of hardware and also was able to pull in an execute (cross compiled) portions of the application processor code within the model, again at a high level of abstraction.

Iron

Assertions not really present in VErilog - the primitive is there but no language concepts to be able to write the assertion in a declarative manner. Will talk about declarative constructs tomorrow.

@eckorsberg:

As far as I know SystemC is only rarely used. It seems to me like a lot of people want to know about it, but it is not used. I assume that most engineers do not get the power of this library and the concept beneath. It enables you to do the step form the algorithmic level to the RTL level very easily. That's beacuse it supports both TLM and RTL. But I guess there are still a lot of misunderstandings, because most engineers come from either the software side OR the hardware side. There are only few out there who bring both together.

Iron

The response checker wouyld know how to check that two packets are consistent, whereas the scoreboard contains a repository of the packets that should be seen on the output. A reference model may also be required that explains how a packet gets transformed.

 

SystemC is the language of choice for high-level models and virtual prototypes (which I haven't really talked about). However SystemC no good for verification and likewise, SystemVErilog no good for high level modeling (extreme view - lots of overlap).

 

Hi Brian..Could you tell the difference between scoreboard & response checker?

Iron

Positive verification is making sure functionality is demonstrated to work. Negative verification is making sure that bugs do not exist.

 

I had not mentioned white box/black vbox differences. With white box it assumes you can see everything in the design. With black box it is invisible - you can only see what is on the pins. Assertions can be written that sit inside a black box and identify errors internally, thus making the innards more visible and highlighting problems when they happen rather than waiting for propagation onto the output pins.

 

thanks Brian - I look forward to tomorrow

Iron

At the system level, it becomes too difficult for constrained random to find useful tests. Maybe I want to ensure that I can take a picture using my devices CCD sensor,. pass it thorugh some DSP functionas and display it on the screen. I would write the code to run oin the procesor, or use production code and the stuimulus to do the intended function. I can check that the image produced is correct.

Could you tell what is the meaning of term positive , negative & formal verification? I missed it..

Iron

Is SystemC still an infrequently used tool in regard to Verilog and SystemVerilog?

Iron

Assertions are used for whitebox verification. What other formal veriifcation techniques can be used to improve the observability in the design ? Can you suggest how one can use assertions in verilog ?

Iron

Seems like a lot of people still using VErilog. For those Janic does have a version of the book that deals with VErilog, but a lot of constrrained andom is not supported properly by those langauuges. We will talk about the new concepts added to VErilog tomorrow when I introduce SystemVerilog.

 

hi Brian,

i did not get the use of directed tests for SoC verification. Coulld you elaborate on that?  Please excuse me if i posed the question incorrectly

Iron

Thanks Brian and Chuck another great presentation.

Iron
Thank alot, nice presentation
Iron

Thank you for another excellent presentation

Iron

Packets get dropped when the design doesn't work, or when it is dfeemed ok to drop them. Maybe it is a quality of service issue that says all low priority packets do not have to get delivered. They can retry when the network is less busy.

Thanks Brian, good presentation

 

Iron

Brian,

Thank you.  I am learning much more than I was prepared to learn.  

Iron

Thanks a lot for the nice session. 

Iron

Hi Brian..Could you tell the difference between scoreboard & response checker?

Iron

Thank you. See you tomorrow.

Iron

Thanks Beian #2,,,lol

 

Iron

Brian thank you for today's presentation

Iron

Thanks Brian for the presentation.

Iron

Thanks Brian. I am using systemVerilog.

Iron

Thanks very much Brian & Chuck,good presentation

Iron

Great presentation, see you tommorrow

Iron

Thank you, Brian! Much to think about...

Iron

thank you for the session

Iron

Thank you Brian, another excellent presentation!!

Iron

Code-level simulation.  Board-level functional testing.

Iron

We use functional testing for board level and product verification

Iron

I am using Verilog simulation

Iron

Verilog simulation with Perl, C and verilog models

Iron

Call and software taps

 

Iron

For board level testing we use functional testing. 

Iron

Verilog Simulations, with Direct test

Iron

Do the sub systems interfere with each other?

Iron
in next designs we will use constrained random tests
Iron

We have used CRV. We found it very useful

Iron

How do packets get dropped in between?

Iron

have not used constrained random tests

Iron

Haven't used this yet.

Iron

I have in the past. The challenge was conflicting constraints.

Iron

Can we use assertions in Verilog?

Iron

Have not used constrained patterns

Iron

Not used constrained patterns

Iron

not using constrained patterns

Iron

Have not used constrained patterns.

Iron

Have not used constrained patterns

 

Iron

Use a spreadsheet matrix as the scorecard

Iron

not using constrained patterns

 

Iron

How efficient is this code and functional coverage check?

Iron

@kentj....thanks....seems ok, now....

Iron

Probably a browser version.

Iron

@Deb C:  Don't know.  The problem lasted several weeks and I do a virus scan every week.  The problem just went away.

Iron

@ Kentj Interesting....never had this issue before...I wonder if it is caused by some evil software I loaded

Iron

@Deb C:  For a while I had to refresh my browser between post just to get them to go.

Iron

I am in test I use the results of the methodology.

 

Iron

Any real time scenarios where this is implemented?

 

Iron

Not currently using directed test but have in the past.

Iron

Interesting....think I need to have a code check on posts....last one disappeared into the either, as well.

Iron

yes I am using directed tests for corner case functionality checks.

 

Iron

Possibly could have used it in the past

 

Iron

Have used directed test and code coverage

Iron

In the prototype I put code in that will tell the host when it accesses the different functions.  They are removed for production.

Iron

Not using Directed Tests

Iron

I have used directed simulation test with code coverage criteris in the past.

 

Iron

Directed tests. Have used code coverage in the past, but not recently.

Iron

A form of directed test with code coverage

 

Iron

We are using direct test, with Code Coverage.

Iron

Not using directed tests & code coverage

 

Iron

Good evening from Iasi, Romania

Iron

Hello from Cedar Park TX

Iron
@wonohkim - Please try using Firefox or Chrome if you aren't already. Many users experience problems with the audio when using IE.

 

My other post was lost...strange

Iron

Hello from Western Michiga

Iron

@Alaskaman66 seems ok

 

Iron

Audio kept disconnected

Iron

Hello all - Audio is live!

Hello from Albuquerque.

Iron

Almost time to start

Iron

nelso7926 from Texas

Iron

Sorry - I'm a jerk.    :)

 

Iron

@kenm53 - Rub it in, why don't ya?

Iron

Too hot in San Diego - it's pushing 74 degrees already.

 

Iron

Almost ready to begin...

@MazianLab:  The problem with the DOS version of OrCAD is my designs are too complex now to fit in 64K of memory.  Heavy disk usage on a 40M hard drive.

Iron

Regarding FaceBook: Yes, there is a Facebook page. Click on "Follow Us on Facebook" at the top of this page. That will take you to the CEC Facebook page.

Blogger

Good Morning from beautiful Valdez

@Kentj, I used to work with ORCAD 4 and POROTEL 6 in 80s. Those softwaes were very powerfull.

Iron

Design News sends me emails about upcoming classes.

Iron

Good Morning from CA

Iron

Pennsylvania, reporting for duty, sir!

Iron

@Charles Murray: Do they have something on Facebook to follow?

Iron

Florida in, and out. I will be attending a webinar on encoders in this time slot today. But I will come back and give a listen later. Have fun everybody.

@brian_bailey - Enjoyed your blog entry. "It's not chip science!" Indeed.

Iron

Be sure to follow @designnews and @digikeyCEC on Twitter for the latest class information. We encourage you to Tweet about today's class using the hashtag #CEC.

Blogger

As an example @tariq. Mentor has both a constrained random solution that they market the heck out of andf a graph based stimulus generator. Their own analysis shows that the graph based produces vectors that achieve the same coverage using 1/10 of the number of vectors. Needless to say they dont market their other solution very hard, and I even believe that their graph based solution is nowhere near the best solution possible.

Hello everybody.

Hello Brian!!

Iron

I liked OrCAD before.  I have a DOS version on an old computer that costed as much as the computer back in the '80s.

Iron

hi brian,

sorry for asking ahead 

whats wrong with constrained random verification when it is mentioned that it produces 10x wastage?

 

We can take this question after the cast if you like

Iron

I've noticed that a lot on companies that know their products cost too much.

Iron

@Kentj that is a little surprising. Seems as if they should make it as easy as possible to make a buying decision.

In order to find the price of the complete versions you need to actually order them.  They don't just come out and say how much the different versions are.

Iron

I downloaded OrCAD 16.6 Lite and I will need to simplify my simple designs a little to get it to work.  It only accepts 50 parts.

Iron

Please joing our Digi-Key Continuing Education Center Linkedin group at http://linkd.in/yoNGeY.

Blogger

The streaming audio player will appear on this page when the show starts at 2 p.m. ET today. Note, however, that some companies block live audio streams. If you don't hear any audio when the show starts, try refreshing your browser.

Blogger

@tariq786 A little. Have to get another blog written before we go live and 15 minutes before I have to start the broadcast prep.

Be sure to click "Today's Slide Deck" under Special Educational Materials above right to download the PowerPoint for today's session.

Blogger

Hello all from rainy Richmond, TX

Iron

Hello from cloudy Atlanta.

Iron

@Brian -- Hah! FutureThought -- shades of Orwell!

What will he say? Hmmm... Popcorn time!

Iron

Hi Brian

Would you have time before the class to discuss something?

Iron

@DaveWR

It only LOOKS like a tree... it is really CO2 LASER..  Un down

Iron

@brian_bailey Bwa ha ha ha!  :D

Iron

Just under an hour to go. Better start thinking about what I am going to say :)

@RMRSS You're pointing to a tree. Better hope NK is not locked and loaded or that tree is history.

Iron

Hello from Sunny SE Lake Simcoe Ontario, Canada, eh?

Iron

hello from Austin!

Iron

Good afternoon from Tornoto.

Iron

Hi from a rainy Austin, TX

Iron

Hi from rainy Panama City, FL

Iron

Greetings from Raleigh, NC

Iron

Logging in from Chicago!

Iron

Good morning from Oregon

 

Iron

Good afternoon on the East coast now.

Iron

Good morning from CA

 

Iron

Good morning from Edmonton, AB

Iron

Hello all.  mixed 29F 43.29°N 77.79°W Elev. 600ft

Iron

No Professor, Thank You!

Iron

@Jacko-07 - Want to give the lecture?

 

GOOD MORNING from SUNNY  42.35N,71.06W....14 slides viewed! 

Iron

Good morning from Mobile, AL

Good morning!  Looks like everyone is looking forward to part 3!

Iron

Good morning from NY.

Iron

Good morning from GA

Iron

good morning, everyone

Iron

Who's watching the watchers?  It's turtles all the way down. ;)



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