Heavy Copper circuitry is something all engineers should be considering in their design. In PTH minimum thicknes should be 1.2 mils. Heavy copper tracing can not only add strength to your traces, it also aids in convection cooling. There is obviously a higher cost involved because of higher plating times however in situations where failure is not an option, its the best way to go. We manufacture heavy copper circuits for military applications mostly as well as high voltage systems. Bottom line if you need high reliability.. go with a heavier copper. Check out www.omegacircuits.com for more info.
It is nice to have more advanced and high endurance PCBs out there, with more Ampere rating. I recall working with comercial PCBs for my final year project. The H bridges of a BLDC motor were made by us on a commercial PCB. When the load used to increase(around 16 amps) the copper wires used to melt and burn the PCB.
I hope having more powerfull PCBs will cater for higher power applications in Industries.
I definitely see the advantages of the higher current carrying capacity and improved thermal management. Copper does have a cost associated with it and I was wondering what the cost impact would be. In what situations would this technique be more cost advantageous versus using other, more conventional techniques?
The PowerLink can be defined as you described by adding an extra Gerber file such as 1A, 1B, or what ever naming convention makes sense to you. The often easier alternative is to use the fab drawing to identify areas of thicker copper. Typically these areas are obvious because the track widths are normally much larger.
In my personal experience, when designing PCBs the concern is centered around high frequency effects. This is a different realm and the artcicle is very informative. I think that one often stays away from high current becuase of the typical types of copper thicknesses that are often used.
My guess is you would create a layer for each different thickness. From reading the article current carrying vias would benefit a lot from this. Basically defining an additional layer in the layer stack associated with those vias would give you this. This is not unlike what you do when you want peelable mask on parts of the PCB.
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