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thanks once again sir brian for a wonderful and well informative lecturing to us eventhough this is already from archived, still, is a good to look back for reference as well...

tomorrow, i will continue the topic till end for the alloted 5-days classes...

thanks again to digi-key and design news for giving this kind of opportunity...

goodnight!

so, almost finishing now on slide 12...

thanks for a well informative lecture to us...

correction, slide 10...

i am now in slide 20...

i am now to begin the lecture of sir brian with slide 2...

i am now downloading the slide of the presentation to go through while sir brian discussing the topic...

good evening sir brian...i am here for your lecture...

design challenges are for hazardous locations, temperature extremes -40C to +85C and vibration/shock

Iron

Typical products are single processor uC or DSP. The technology includes mostly digital and RF circuitry, some analog processing.

Iron

one more role.. develop and implement test plans for new product verification.

Iron

Role within my team: We are a small R&D team with many hats. My role is at any time one or more of the following.

designer for electronics and embedded control, software and hardware tester, develop the functional specs and user interface for a new product, investigate product improvements, verify that the product meets all specs and does not introduce unintended features, technical writing for product manuals, user guides, installation and troubleshooting instructions.

We are also the product support experts for the service department and customer trouble calls.

Iron

Hello all from chilly Edmonton, Alberta. 1st May and still snowing!

Iron

I work in firmware mostly in the hardware interface side of things

Iron

My part is work with Hardware team.

Iron

We use some formalized verification but I don't think its adequate 

I'm not working on any designs at this time

My role is basically software based to actually write/repair the higher level software which interfaces with these lower level chips in their board populated state

Hoping to get caught up for the week today

Internet problems prevented a live connection

Iron

Thanx Brian , perfect intro. and prof.

Good intro.

Soc, FPGA's.

Management, Project Engineering, Architecture and Specification, System Integration, Transition to Production ...


Would like to see a slide or two in presentation one on approach going from 1) Specification to 2) Test Plan to 3) Modeling approach.  Then two or three slides at the end of the session (class 5) amplifying and summarizing the entire approach - not really outside the scope of the presentation, but just to tie the entire process flow together ...

Small FPGA design - control circuit.

Electronics Engineer - development / manufacturing / engineering

Validation -> Test -> Verification

THanks Brian, Chuck, Digi-key, et.al.

Iron

Thanks a lot Brian!

Iron

Than you alot Brian! Very nice session

Iron

Thank you very much Mr.Brian, really pleased with your cooperation!

i think a course on formal verification as a next step would be really nice. Brian could you see its possibility in the near future?

Iron

Well, I do have to go now, but willbe back on here 15 minutes before the lecture tomorrow.

 

It was about 9 yrs. ago so they were not as sophisticated but it performed it the calculations as prescribed so results were valid for the ASIC but the resulting values did not produce the desired effect, so the bit shifter was born.

Iron

Analog and mixed-signal does require some very different methods, such as parametric sweeping. This is very specific to analog and not common in digital designs.

 

I want to formulate methodolgy for regularly testing of these products..

Presently we use software simulators like Proteus, but rely more on prototype testing, rather then emulated methods

At least not in this course - perhaps that is another one we should do...

It is focussed on verifying a design before it has ever been built. Verifying a manufactured product is more a mtter of test and I will not cover that - sorry.

Do you currently model and simulate your designs or is this something that you dont want to do? If not, then you will only get concepts rather than detailed answers from this course.

Energy Meters, Automation equipments etc.

I am leading embedded designs based on microchip PIC 

industrial energy and power based products

Eg, Line conditioner, Remote Monitoring and reporting, data loggers

There are many fundamental concepts in verification that apply to all forms - it is the econmics that often change the most.

VLSI chip verification is the most stringent form of verification because of the cost of getting it wrong. Some poeple do limited amounts of PCB verifciation and system verification is required by many mil/aero project. What kind of design are you working on Mohammad_Zohaib?

 

The slides seem to depict that the methodologies are more focused towards "VLSI design verification", hope there is a generic method of verification that can suit hardware design as well..

I can see the slides perfectly now. Thanks a lot.

Iron

what about the hardware question posted by Mohammed_Zohaib?

Iron

Thank you for the presentation..

thanks.  see you tomorrow.

Iron

Thanks Brian, I look forward to tomorrow's presentation

Iron

Thanks everyone for listening in today. I will be around for a few more minutes if you have other questions

Brian, Are we going to cover verification methodologies focused towards hardware design? OR are they generic and can be adapted to all designs?

Controllability/observeability - partly dealt with by doing a lot of block level verification where the problem is not so bad. Have to restrict the system level tests carefully because of the time they take. Also some people use emulationm or prototyping to speed up the process. We will talk about those tomorrow.

https://verificationacademy.com/

Great Presentation and talk Brian! 

Question: In the need for verification you talked about controllability and observability due to complex design challenges. How we engineers trade off when trying to check the various blocks for functinality vesus verification time?

Iron

I will mention formal in several places including in the SystemVerilog session and tomorrow in models and their execution. Will not however have time to go in depth. That could be a course all on its own!

Brian can I get that Mentor Graphics link

Iron

some discussion on formal verification would be really nice in the forthcoming lectures

Iron

The chat log will sty here forever.  The chat logs are still available from the first sessions last year.

Iron

cut and paste seems to work.

 

No idea how to get a copy of the chat log. Sorry.

Hi RMSS - surprised that worked in verification? It means they did not have good enough checkers.

 

yesp please cover slide 16 tomorrow with real example. The arrows are still confusing

Iron

Brian, Can we get a copy of chat log? Thanks

 

Iron

OK - will try a concrete example for tomorrow.

Thanks! Brian very good presentation!

Iron

Is slide 16 clearer now? If not then maybe I can go over it a little more tomorrow.

 

Brian,The last test I worked we used what we called requirements verification matrix based on design and worked through to develop tests from this.  I remember one time the design guys had a case where they dropped what they thought were the least significant bits but where actually the MOST significant.  It was a little endian big endian thing.  It verified Ok in simulator of course but not in operation.

Iron

Brian, can you put a real example for slide 16 for tomorrow's lecture.

 

This is just  a suggestion.

 

Thanks so much for every thing

 

Iron

Random testing comes in handy.  When I worked at Fluke, random testing showed HP on the display of one of the meters.  That got fixed.

Iron

It is like dealing with the what and the how question. Validationm is what, verificatiom is how.

Validationm is checking that a specification is correct. Verificaion is making sure a specification is implemented correctlty.

 

sorry for my bad typng there...

could you talk about difference between verification and validation? Please

Iron

When we very a blkock in the conext of a system, we are in effect making sure that the sepcification was understood and the specification is consisent. In other words we are beginning to do some validation up front rather than at the end where it is done today.

Thanks Brian for the wonderful presentation.. 
No not really, we try to follow the approach of handing over same specs to two guys and then basic checklist procedure to verify functionality

Then when the design gets progressed, detailed models can be inserted into the system model and verified in the context of the rest of the system.

 

could you please explain slide 16 again?

 as it is not very clear

Iron

Slide 16 - yes sorry, it was rushed as I was runing out of time. IN the system integration flow we put together high level models to create a system model.

This can be verified standalone.

Extremely informative. Look forward to the rest.

Iron

Thank you so much, Brian. 

Iron

Thanks for the lecture

Iron

Brian,Thanks very much

Iron

Thank you Bran for an iteresting start to the week.

Iron

Thank you, Brian! Very interesting.

Iron

could you please explain slide 16 again?

 as it is not very clear

 

Iron

software simulation only at this point

Iron

Not yet, too much time is spent on machine debug

Iron

Brain, thanks for presention.

Iron

Thanks alot, look forward to tommorrow

Iron

Semi formal method.  Some in house some formally purchased SW libraries.

Iron

unfortunately not. Just verification with Perl, C and verilog models.

Iron

Thank today's presentation Brian

 

Iron

Very informative lecture

Iron

Just Verilog Simulation

Iron

could you please explain slide 16 again?

 

Iron

pretty much manual testing

Iron

Brian! Thanks for excellent presentation.

Iron

Not yet - still in rough software simulation mode.

Iron

yes i am using formal verification

Incisive

Iron

ARM and DSP Designs

Iron

****** Slide 15 *****

Iron

RTOS, FPGA, MCU, PLL RF, Mixed signal 

****** Slide 14 *****

Iron

Depends on the client. Mixed signal, FPGA, wide variety of MCUs and SoCs. Many medical devices, consumer products, and security devices.

Iron

ARM Cortex based design -- gathering analog information -- feed network of analysis machines

Iron

Very mixed signal, seldom any processors as such. 

digital, quad-processor, multiple FPGAs

Iron

Digital, FPGA acquiring and processing data from High Speed ADC

Iron

Analog & MicroControllers

 

Iron

FPGAs would really simplify my designs.  Using two processors and about 60 other ICs building high speed test equipment.

Iron

Mix signal, single processor

Iron

CPUs for parallel processing.

Iron

Microcontroller based embedded systems: PIC / ARM based
Intelligent reporting and monitoring

Any topic on Low-power verification?

Iron

New processors, ARM, x86, lots of different periferals.

little D big A custom SOC, no processor

Iron

digital, one processor, multiple 1G Ethernet controllers, SAS and Fibre Channel controller chips

Iron

Mixed Signal Audio/Video

Iron

Core processors and DSPs

Iron

5 to 6 M Instances , Mixed Signal SOC

 

Iron

Fairly complex, but if I tell you the detail... (well you know)

Iron

Digital designs for telecomunication (base band) using FAPGs

Iron

Mixed signal, 2 CPU Cores, FPGA, ASIC

Iron

96-150 ucontrollers

Iron

digitial, > 4 cores, network Phy's

Iron

Software design and implementation

Digital system design using FPGAs and CPLDs.

Iron

IP verification

 

Iron

****** Slide 12 *****

Iron

Supply Chain and MFG for a medical device company.

Iron

Packaging Automation Developer

Iron

Design and verification Engineer.

 

Iron

I'm a PHD student and design engeener

 

Iron

I used to work on verification phase for systems.

Iron

VP of medical device division

Design & Development focus.

Iron

 Field service- functional verification for devices returned from the field

Design and Verification of ssoftware and Hardware

Iron

I am a digital design engineer, does block level verification and, when needed, top level verification.

Iron

Verification of sub blocks with Verilog Simulation, Chip level Simulation 

SOC Timing Verification

Iron

Lead Design Engineer - R&D

Circuit board design for x86 processors

 

Iron

Systems Engineer - Design + Verification of FPGA Cpres

Iron

hardware and software designer

Iron

Hardware / Software verification

 

Iron

Working in manufacturing  - Process Engineer
with masks/trenches

Looking to learn more in desgin

 

Iron

I'm down in the trenches. Embedded systems design, development and testing. Mostly firmware (software).

Iron

embedded software design

Was in SW QA and trying to move into development.

Iron

Industrial Design Management Consultant

Iron

Design team - early days.

Iron

Production test engineer

 

Iron

Currently in management

Iron

****** Slide 10 *****

Iron

Used to be in verification for several years...

Iron

As the sole engineer, I do it all.

Iron

Design team working primarily hardware at this stage, although I do write code when needed.

Iron

I am in the design team.

Iron

embedded firmware and systemC modeling of SoC

 

Iron

i m design + verification

Iron

FPGA/ASIC designer

Iron

@kkonesky:  It still is.  We use it for test equipment under test and components in receiving inspection.

Iron

DUT used to refer to Device Under Test.

Iron

****** Slide 7 *****

Iron

****** Slide 6 *****

Iron

****** Slide 5 *****

Iron

Below the Apr 01 - Day 1: Fundamental Concepts

Iron

If you don't see the audio bar just under Apr 01 - Day 1: Fundamental Concepts, Restart your browser.

 

Iron

Top of the page you should click on the Audio Icon.

Iron

Now it's good

 

Iron

****** Slide 4 ******

Iron

Hellow from Houston, TX

Iron

Not seeing where to get linked into the audio? Where is it?

 

Iron

****** Slide 3 ******

Iron

Hello from Wisconsin

Iron

Hello from Cleveland Ohio

Iron

****** Slide 2 ******

Iron

Hello from Eugene, OR

 

Hi all - Audio is live!

Hello from sunny Toronto.

Iron

Good Morning/Afternoon/And Evening from Newark DE.

Iron

Hello from Placentia CA

Iron

Audio is loud and clear...

Iron

Hello this is Garth in Texas USA

Iron

may be reload page?

 

Iron

has the sound started yet?

 

Iron

Hello from Ottawa ON

Iron

Brian: Yes I have an idea about the need for system verification. We were maintaining Motorola MSF-5000 UHF base stations, and occassionally we would get a failure with an obscure error code. I called Motorola engineering and after sending them the exact werror code, asked why they didn't publish an error code library. He said even the engineers didn't know what the error cosdes meant, or what exactly caused each one; they had to run down the hal to the softheads and ask them. The codes were altered with every production version. Talk about no one steering the ship.

Hello, from Redmond WA

 

Iron

Hello everyone from Manasssa, Virginia

Iron

Hello from Cedar Park TX

Iron

Hello from Albuquerque.

Iron

Good afternoon from sunny St. Louis (finally!)

Iron

Hello from Fortaleza, Brazil

Iron

But we got 55 inches of snow last week..

Good Morning from sunny Valdez Alaska

Hello from Michigan

Iron

We did hit 80 yesterday, and rainy.  Super humid.

Iron

I spent the last month in Central Minnesota so 34 deg seem warm

Iron

Hello from Huntsville, Al

Iron

We almost hit 80 yesterday!!!!! Incredible day!

 

Good afternoon from Western Michigan where it is asunny 34 deg F

 

Iron

Wish I was back there.  I'm from Marysville, WA

Iron

Happy Monday from Central California

Iron

Weather in the Pacific North is wonderful!

 

From the perspective of large systems, software, yes. From embeded, not sure.

Iron

@brian_bailey:  Could start with the weather.

Iron

Does anyone have a clue what I am meant to be talking about today?

 

Hello from Baily's point North Pole!

Iron

Florida in the house.

Iron

You notice that Design News/Digi-Key doesn't say the first 25 attendees will be getting Starbuck gift certificates anymore.  I'm assuming they're picking attendees at random.

Iron

That's RichmonD, TX

Iron

Hello from Richmon, TX

Iron

@farhad00110 - At 1:00 PM (assuming you're on Cental time like me), a sound bar should appear at the top of the page. If it doesn't appear, refresh your browser page. It doesn't start automatically. You'll have to click the play button. There's no video. You'll need to download the slide deck above and follow along. If you don't have Power Point, you should be able to download a Power Point Viewer for free.

Iron

Hello from Reston, VA

Iron

I think an audio feed starts up once we actually get started.

 

Greetings from AR, can anybody please explain how to get into the lecture session once it starts?

Greetings from the Windy (and chilly) City of Chicago.

Iron

PowerPoint saved from 2010. I am guessing it is converted by the site.

So close to Day 1 concept.

Iron

A VerilogQuickRef.PDF hopefully the link makes it though

stanford.edu/class/ee183/handouts_win2003/VerilogQuickRef.pdf

hth

Iron

Good Morning all from CA

Iron

Hello from Chicago

Iron

Hellow morning everyone.

Iron

@r_barlow What part?!  I used to live in Nashville...

Iron

Hello from Tennessee

Iron

@MSalimM


I saved the presentation as a PDF.  I have uploaded it to a file hosting site called 2shared.com.  Some users on this forum have had problems with this site in the past.  If you don't have AdBlock running on your browser, there might be a few advertisement URLs they want you to click on instead.  Just look for the big blue download button for the actual file.

http://www.2shared.com/document/zkWMKJQ4/DN_CEC_Functional_Verification.html

 

Iron

Hello from Sunny SE Lake Simcoe area of Ontario Canada.

Cold and snowy here.

Iron

Good Morning.

I'm having the "PowerPoint can't read the outline from (filename) No text converter is installed for this file type" issue.

For following slides could you save with an updated PowerPoint please. Thanks a lot.

(http://answers.microsoft.com/en-us/windows/forum/windows_vista-windows_programs/powerpoint-cant-read-the-outline-from-filename-no/6d429d6f-b35e-4766-bb10-8fad013c9d35)

Iron

Hello from Scottsdale, AZ

Iron

Hello, Good to be back in the classroom

Iron

Good afternoon from the sunny - but cold climes of Aurora Ontario

Iron

Good Morning from sunny Panama City, FL

Iron

@Brian: April Fools. This is a cake baking seminar.

Iron

Monday is shaping up nicely. Happy Monday!

Iron

Howdy folks!!!   STL @ ARI.  I love baseball!!!   (It's been a long, cold, lonely winter...)

Good morning from sunny Chicago, a high of 39 degrees F (4 degrees C). A perfect opening day for MLB.

Blogger

Good Morning from SUNNY Boston!  Red Sox vs Yankees Opening Day; GO SOX!

Iron

Good morning y'all!  Had some snow on the ground this morning, after a weekend filled with sun and 70s!  :/

Iron

Good morning everyone. Three hours until I start - or maybe the whole thing is an April fools joke. What didn't they tell me? Hmmmm

 

Good Morning, everyone

Iron

Good Morning from GA

Iron

Good Morning from Milwaukee!

Iron

Good morning from upstate New York.

Iron

Good morning from Mobile, AL

Beware vector driven verification of async digital circuits using event driven simulators.

Amazing bunch of early birds. Spring must be here.

Download slide have a look. Thanks.

Iron

Thanks for the slides

lookin' good

Iron

Eagerly waiting to paticipate in this session

Iron


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