I'm not sure if anyone is still montoring this chat, but if so I have a question regarding device powering. I am having trouble understanding what actually controls the amount of current being delivered on VBUS to any one device. To provide an example - I am working on a design of a device that has a 4-port hub as the direct connection to the USB host on a PC, and from that there are three devices currently connected. When all of the devices enumerate as being bus-powered, how much current is actually available from the host? Does it allow up to 500mA draw regardless of how many devices are actually downstream of the hub, or will it only provide 100mA per downstream device?
I was able to follow along. I imagine several people were spending valuable time trying to find the right slide to look at. I can see the slide numbers on the left side of my screen. A suggestion I have is to verbally identify each slide with its slide number and title. An example would be to say "On slide 14 titled Bus states, it talks about the keep alive signal ....".
Anyway, that was the fastest class I've ever been through, and I think you did a good job of presenting the material. Thankyou
We are brand new to USB embedding and are developing a peripheral that needs to exchange data with a computer. USB 2.0 might be a good start as it appears to be less complex to implement and our data rates are relatively low.
Thanks for presenting this course as it seems to be just what we need at this moment.
@Christian: I was wondering why the standards committee chose to use a completely separate set of differential pairs for USB 3.0 transmit and receive, rather than doubling up at least one of those pairs on the existing D+ and D-? That would seem to increase the contact area within the connector for each conductor and just generally simplify things mechanically and electrically. What benefits were they trying to achieve?
Hi Christian, i'm looking at adding USB to an 8051 design running at between 16-24Mhz to replace the serial port. Is there a simple chip that can be used to add to the design that takes care of the protocol but interfaces into the 8051, i do understand that it would be a low speed solution.
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