There are really no limitations to the die you can include in an RCP design. RCP can accomodate any die, any technology node, and use die designed for wire bond or flip chip.
There are many reasons customers prefer ARM to other 32-bit architecture, but the two most common reasons are energy efficiency and software ecosystem.
To add what Rich mentioned about our involvement in the FDA, CE or any other healthcare regulatory organizations. Component manufacturers cannot certify their parts via these organizations, but Freescale will provide to customers documents from our Quality Management System (QMS). These documents are then provided to the FDA by the end customer as part of their FDA submission. Information on Freescale's quality system can be found at www.freescale.com/quality.
The couple packing technologies I discussed were Wafer Level Chip Scale Packaging (WL-CSP) and Redistributed Chip Packaging (RCP). Wafer level CSP is a packaging technology where the pads may be etched or printed directly onto the silicon wafer resulting in a package very close to the size of the silicon die. RCP is an interconnect buildup technology in which the package is a functional part of the die. The technology addresses the limitations associated with previous generations of packaging technologies by eliminating wire bonds, package substrates and flip chip bumps. In addition, RCP does not utilize blind vias or require thinned die to achieve thin profiles. These advancements simplify assembly, lower costs, and provide compatibility with advanced wafer manufacturing processes utilizing low-k interlayer dielectrics. WL-CSP is the much more common technology. RCP is a technology that significantly reduces size, but the technology is complex and it is only being offered to customers who really value its small size, such as those in the implantable market.
In general, the FDA does not get involved at the level that Freescale deals with. That's usually the responsibility and expertise of the device designer (and associated company). Although Freescale has some level of expertise to help along the way.
In attempting to shrink our next generation design, it has been suggested that we could use a via-in-pad design, even on passive components. This could certainly by of great benefit on bypass caps that only connect to power planes, but can also help with general routing.
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