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good presentation -- good *(simple and clear) slides describing NVIC!!

prioritized and nested interrupts are common in most (medium to high end) applications I've been involved in ...

 

 

very nice presentation

Is it possible to see an example of a shared resource with nested vector interrupts?

Iron

Thank you Paul, very interesting session

Not on these devices.

Iron

@Chuck - yes, have used the interrupts before

Iron

@Chuck - have not used it yet

Iron

Great to have access to the recorded sessions.

Iron

Missed the live lecture due to travel...

Iron

I've never used Cortex

Iron

I finally showed up.  :)

 

Iron

well, better late than never

Iron

@LevitonDave: I suspect that the limit on the number of interrupts that can be pending at any given time is the number of interrupt sources (eg, devices) in your system.

Iron

 

 

CPSID to disable interrupt until task finish.

Thanks.

Iron

Ok See you tomorrow!

Iron

Thansk Paul - see you tomorrow.

I agree that the there is probably no chaining limit. However there may be a limit on the number of interrupts that can be pending at any given time.

OK folks, got to go, all the best, and

see you tomorrow...

Paul.

 

Blogger

chain limit refers to how many one-into-another interrupts can

continue without context switching.

Blogger

Reference documents:

ARM DUI 0497A - Cortex-M0 Devices Generic User Guide

ARM DDI 0432C - Cortex-M0 Revision r0p0 Technical Reference

(From NXP LPC-111x User Manual)

I would think that there would be no limit to tail chaining. If interrupts kept arriving before the stack pop, they would keep being serviced indefinitely.

Iron

what is the chain limit?

 

Iron

Different vendors with different tail chaining limits...

Hmmm, I don't know.... I will try to resolve this

question - as you've got me wondering now myself???

Blogger

Thanks for the session Paul. See all tomorrow.

Iron

The memory for the stack push is that memory which is pointed

to by the MSP (R13)   This can be fast or slow depending upon

the value is R13.

 

 

Regards the timing question:  I have a bibliography as the last slide

of the last day.  I don't think that super-detailed timing is shown on

any public documents that I have seen!  Hmmmm.

Blogger

@WarrenM - Some of these are vendor specific and their documentation needs to be referenced.

Paul Thanks, overall great explanation.

Is it possible that different wenders offer different tail chaing limits?

 

Iron

Where is the memory for the stack push? Is it internal tightly-coupled memory (falling in the 0x20000000 space), or external (0x60000000 space)? 

Iron

@PaulN- Can you point us to a good document (maybe ARM Tech Ref Manual is the correct one?) for the fine details on Interrupt timing and functionality?

Iron

Registers and R3, R2, R1 not being as general as the rest,

yes, these are the defaults for stack framing, one might imagine

that the compiler takes advantage of these first, if one needs more

then manual stack operations are required.

Blogger

thanks for going over the events Paul need to go over interupts just at the beginning...

Iron

Thanks Paul, I know NVIC is Nest Vector Interrupt Controller, what's the exact benifit in real applications?

I am sorry we ran out of time for the SCB, but

I will say a few things about it tomorrow and point

you to places to see more information.

Blogger

Thanks see you tomorrow

Iron

I do not know the chain limit, that is a good

question, I will try to check.....

Blogger

Paul,

How about low power apps?  How dothese stack up corewise?

Iron

GREAT STUFF!!!  Thanks.. See Yoy tomorrow.

Yes, NVIC priority can be changed.  CMSIS can be

used for NVIC setup or you can access the registers

yourself.

Blogger

Howmany lavels of tail chaining is allowd in mo and m3?

Iron

I don't believe that SYSTICK shuts down on a normal

SLEEP - but it may shut down when doing a DEEP SLEEP

Blogger

can I know how to configure NVIC for the priority? can it be supported in dynamically?

Hi, is there a way of download the audio of past lessons?  thanks!

 

Iron

It seems the ARM CORTEX-M0. has a lot of cool features.. How does it compare with other controllers from dirrerent vendores??

will there be expansion of the scb in a leter session?

Iron

Thanks.

Paul,

Is there any difference in what's saved among interrupts ie. registers pointers etc.?

 

Iron

@PaulN: Thanx for the details. If it is a single cycle for each of the registers you list, the other 4 cycles is for the vector fetch and then the jump to the Interrupt address?

Iron

Thanks for a highly enlightening discourse on the M series. Looking forward to the rest of the lectures Cheers

Iron

@pauln: That's intriguing. I assume there are conventions governing the use of general-purpose registers R0 - R3 and R12 so that they are not really as general-purpose as the rest?

Iron

Paul - can you comment on the utility of the Systick timer in light of sleep modes?

The stack frame is automatically pushed by the processor.

Blogger

You can figure the clock cycles from the Stack Frame size plus

memory access times.

Blogger

Thanks Paul - the tail chaining and late arrival were explained in a clear and useful way. The push/pop activities and timing are useful to know. Thanks.

thanks Paul and Chuck --- see u tomorrow

Iron

The core saves PSP, PC, LR, R12, R3, R2, R1, R0 on a stack frame.

Blogger

Thanks Paul and Chuck for the interesting session today.

Iron

wow!very very helpful

thanks Paul and Chuck

Iron

Thank you, very useful info.

Iron

@WarrenM: Who said it's 12 cycles?  Did I miss that?

Iron

Thank you Chuck, Paul, and all.

Iron

Thank you Paul and Chuck !

 

Iron

Thanks Chuck and Paul!

 

Iron

Thanks that was very helpful.

Iron

@WarrenM: likely the core does not save any general-purpose registers. The interrupt service routine would be expected to save anything it uses in that case. So the core just saves things that must always be saved, such as the instruction pointer and status register.

Iron

Thanks very much, Paul!

 

Iron

would like to see more indo on the scb

Iron

@Paul:  Usually each interrupt has independent stack store because of the unpredicitability of the interrupts.  Why no stack storage for chaining?

 

Silver

Still interested in why Interrupt latency is 12 cycles. Is it basically the number of cycles the state frame needs to be saved, plus the Interrupt Vector fetch? There are 13 General Purpose Registers. Don't they all need to be saved? Wouldn't that be at least 13 cycles?

Iron

@Paul: Is it possible to skip the stack frame save/restore?  Is this a control option?

Iron

is tail chaining used when you have 2 or more interrupts of the same priority, or do you pop/push

Iron

How many interrupts can be tail chained?

Iron

tail chaining = tail end optimization for procedures ? no need to execute a return/pop stack frame then a call with push stack frame

Iron

prioritized interrupts are nice to fall back on, but aren't always necessary

 

Iron

multiple alarm inputs and system fail detection would make good use of priority interrupts. capturing all, not just the first interrupt is usefull here.

Iron

@Chuck: use nested interrupts all the time.

Iron

Emergency interrupts in a mission critical application would prepemt any other interrupt such as round-robin concurrent processing time tick.

Iron

Yes- Checking battery voltage level is high priority. Reading sensor, lower priority..

Iron

need priority in interrupts

Iron

some designs would have benifited from nested/priority interrupts.

Iron

@pauln: why would one want NMI or HardFault to be fixed at a lower priority than reset? This forces all the peripheral interrupts to either compete with NMI and HardFault, or to all be at the lowest priority, eliminating any ability to priorize external interrupt sources.

Iron

In the past have had systems with multiple interrupt levels /vectors.  Not currently though.

Iron

Some of my designs require priority on interrupts but most don't.

Iron

used Motorola, ARM, Renesas, and other

Iron

WarrenM: please refer Cortex-m3_technical reference manual:

Figure 5-2 Exception entry timing

Iron

Yes -- doing high speed data collection which requires prioritized interrupts

Iron

@chuck no current requirement for prioritized interrupts

Iron

Yes - typically needed for multiple competeing actions that have an inherent priority.

No, I have no system design using ARM at all now

Iron

sometimes need priority in interrupts, but not currently

 

Platinum

No specific requirement for nested interrupts.

Iron

for audio, in the wors case, login again

Iron

audio back... the radio decided to pause itself - thanks

Silver

audio OK here. try browser refresh?

Iron

@lsleguard Audio good here

Iron

Yes I am also wondering about hte 12 cycles too

Iron

just lost audio...anyone else lose too

Silver

@Wen_Tyco: Thanx for the info. Can you explain why it is 12-cycles?

Thanx

Iron

How many clock cycles takes to fetch data from RAM or program memory, or flash memory/EEPROM?

Iron

it looks like the cortex memory is organized as bytes. the offsets on slide 14 are 4 byte increments per vector.

Iron

a 12-cycle latency from asserting the interrupt to the first

instruction of the ISR executing

Iron

Hi all, I late too from Wilmington NC

Iron

oh Hi all, rudely late from California

Iron

Can you tell us how many clock cycles interrupt latency is?

Thanx!

Iron

@pauln: LevitonDave's assertion that SysTick timer shuts down during sleep actions suggests that it can be used for some relative timing operations but is useless for absolute timing such as time of day or even fixed duration delays. Please comment on how to address those other timing needs.

Iron

@QUESTION: Paul is probably being very detailed in his explanation. Isn't the NVIC the normal ver=ctor table used since the bigining of times in the start of x86 family?

Iron

Hi all, rudely late from California

Iron

@raony.barrios: Audio has been running for about 4 minutes. Try refreshing your browser, eg, press F5.

Iron

@paul: is the stack frame pushed automatically by the processor? (slide 11)

Iron

@luizcosta -- I know the M3 Cortex units from TI can use a 32 bit register as an RTC -- on SOME of the units. L4F for sure -- maybe...

Iron

used Motorola, ARM, Renesas, and other

Iron

Yes, Arm 7TDMI and other processors, No for M0+

 

Silver

arm7, no interrupt experience. lots on 8-bit uP, uC

Iron

Used Interrupts on Cortewx M3

Iron

@Chuck: have not used any interrupts on Cortex-anything devices.

Iron

Yes - ARM7 interrupts - pushed most to the slower VIC.

Interrupts in general have impacts on Real-time actions :)

I have only used on Motorolla 68hc12

 

Iron

no, hopefully in the near future

Iron

I actually have no experience on ARMs at all.  But my next product will likely use an ARM...

 

Iron

no, but have on 8-bit micros of course

Iron

Have not used ARM processors.

Iron

Have used Interrupts on other MCUs not ARM.

Iron

@danlefluer - age 8 - wow thats great. I fell like I missed my calling since I went into software engineering years ago, but now finding the electronics super interesting and fun. but have not been able to get any interested from prospective employers. I thinking, as you say, the electronic jobs are just getting less and less. I've even been thinking about volunteering to company's just to get some experience.

Iron

@Paul: What in hell is an M0+?  You keep referring to things you haven't alked about. 

Iron

@QUESTION: 

What do we do if we want seconds, minutes, hours such as in an energy application? Do we have to use software based delays?

Iron

systick not used on cortex, but have used system timer on propellor chip.

Iron

Gotcha on SysTick timer is that it shuts down during sleep actions.

yes, used as OS system tickon M3

Iron

Have not used ARM, so never used SYSTICK. Usually need to use a timer for that function for other micros. Having a timer/counter optimized for that makes a lot of sense.

Iron

I'm sorry, is it a prerequisite to have used ARM cortex processors before attending this course?  If so, some notice would have been appropriate.

Iron

When you get to the NVIC I'd like to know how many clock cycles it takes to enter an interrupt Routine (and then how many to return). The CPU is described as 'low latency' but I'm having trouble finding out exactly how many clock cycles it takes...

Thanx!

Iron

No Cortex experience "yet"

Iron

Has not used SYSTICK

Iron

Used SYSTICK feature? Yes on M3.

Iron

have not used a cortex based device to-date

Iron

Sure, systick as Os time

Iron

yep i used it on cortex m3

Iron

Not used tick feature.

Iron

@Chuck - have not used the systick

Iron

Using on Cortex M0 device

@jl, built my first fox hole radio when I was 8.

Iron

@danlafleur - thanks for the reply. me too interested in electronic proj and embedded sys and control.

Iron

@jl, also looks like electronics jobs are fewer all the time.

Iron

@jl, sorry, was pulled away. My comment refers to electronics as a hobby isn't what it was before. Every Popular Electronics project was a list of Radio Shack part numbers. Building electronics projects for the fun of it has been replaced with other things for most people.

 

Not for me though. I'm still strongly interested in electronics and embedded control.

Iron

@raony.barrios: Audio has been running for about 4 minutes. Try refreshing your browser, eg, press F5.

Iron

Audio is up here.  A little quiet, maybe, but here

Iron

audio loud and clear

Iron

is the audio working yet?

 

ARM states that these perifs are optional on the MO-M3

Hello all from Upstate, NY.  75 degrees and great. 

Iron

Greetings from Austin, TX!

Iron

Hi Chuck - was there something about a laser pointer? is this for the first day or any day?

don't mean to be posting in bold letters...not sure what's happening

Iron

Good afternoon, Paul.

Iron

Hi Chuck, Paul and all.

Iron

@danlafleur - "electronics has gone away" - was curious about your comment. do you mean you have moved on past electronics, or there is less and less electronics jobs, just curious

Iron

I made it right on time for a change

Hi from Sunny Albany New York

sonora - is that where you sleep through the lecture :)

hello from sonora calif

 

Iron

I'm a licensed freelancer, circuit jocky, and general spark for fun type of engineer. Don't touch my work unless wear rubber gloves.

Howdy from Fort Worth, @ 83 degrees.

Iron

Hello from Atlanta. East-coast represent!

 

Iron

Hi from Portlandia (Wondering when Software PE will be viable in Oregon)

Another San Diegan too in the house

Iron

@rhall007

HA! A fellow cheesehead from WI!

Iron

The State of Ohio has some VERY long-standing licensing exemptions for "engineers".  I would not want to push the issue,  and certainly NOT push the politics.  Even the Patent and Trademark Office does not understand "software", so I can't expect our legislators to do so.  

Iron

@danlafleur - what do you mean "electronics has gone away"

Iron

Good afternoon, folks.

Iron

@Rob Lake. Do you have your license yet? <chuckle>

Is what that should have been. Check out that link later folks and read about licensing. This has been a long time coming and is approaching ion Ontario as well -- through the Trades Council.

Iron

Is there audio or video for the lecture?

Where is the link?

Iron

@Dan Lake. Do you have your license yet? <chuckle>

Iron

Where is the lecture today

 

Iron

Hello from Minneapolis.

Iron

Hello from Sunny (SE) Lake Simcoe area of Ontario Canada

Iron

Hello from Boston MA, nice 81 °F.

Iron

hello from SUNNY MIAMI!!!

@RobLake, I'm happy to see greater interest in embedded processing and firmware. I was quite interested in electronics as a hobby, long before becoming a professional in the field. Electronics has qone away, but experimenting and learning with all of the really affordable embedded processor kits is exciting. lots of open source makes it easy to try some really challenging projects for little cost.

Iron

checking in for the presentation! :-)

Iron

Good Morning/Afternoon from Sunny San Jose, CA It's 63 °F now and will reach to 77°f this afternoon.

Iron

I'm here as Co-Chair of the Firmware Engineers of NE Ohio group.  Looking for topics for future meetings here in Northeast Ohio.  More into at www.firmwareplanet.com , a parallel effort of the rapidly-growing interest in firmware and embedded systems here.

 

Iron

by the way, I did get an email reminding of today's session. I don't recall getting any others this week.

Iron

Good morning all from Edmonton, AB

Iron

Hi all!  Looking forward to today's lecture

Iron

Hi there...oops!missed yesterday's class...i'll download the slides and try to catch up before today's class starts...

Iron

Hello from sunny Cleveland Ohio..Logged in early..just in case..



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