Max, I noticed when I try a link (and lose this page) and then try to come back to it, it starts SLOWLY rebuilding the conversation. But if I right-click and "reload" or "refresh" at that point, it almost instantly jets straight to the top of the list of posts. Maybe it will work for others... (i'm using Chrome)
I was just being funny.... I don't even use an oscilloscope, but I stumbled into that video and thought it might be a good resource to share. I do sympathize with people trying to learn new subjects, Sometimes it seems like there is too much info on the internet, a lot of it very specialized, and it can be difficult just trying to find a GENERAL INTRO on something that covers the bases without going too deep. That is one reason I appreciate DigiKey and Max for doing a series like this.
pcbJack - I'm the opposite; much rather read than watch (usually, anyway) - why take 5 minutes to watch something I can skim and read in 60 seconds? (but then, I'm old, as my kids keep reminding me...)
Errant - that doc pcbJack posted shows a bunch of equations to figure it out (page 4) but says rule-of-thumb is 5X the fastest clock in the system. That jives with my memory (but I didn't post an answer 'cause I wasn't sure my memory was right...)
I'm sorry everyone -- it will take me ages to recover (like 30 minutes to reload all the messages to come up to date) -- I'll have to sign off now -- I hope to see you tomorrow for the final session...
Re "Cray on an FPGA" .. it's easy to forget how far we've come so fast -- the article I mentioned says "1983, the Cray X-MP was the world's fastest computer -- Dual CPUs, 16MB of RAM, and a peak performance of 400 Megaflops" ... not so impressive by today's standards...
OSC. BANDWIDTH: It is simple. Decide how manu periods of the fastest clock on a digital circuit/system and/or the fastest harmonic component of an analog signal you want to reproduce and "measure" sith clarity on the osc. screen. That is the answer. Am I close, MAX?
yeah, I'm kiddin' ya... but seriously, I just fouind a LOT of info about that just with a general search on "oscilloscope bandwidth". The answer i saw more than once, specifically, is that your o-scope should be at least two times the highest frequency in the device. I'm sure there is more to it, just telling you what I saw
I asked Mike Dunn who is Editor in Chief of www.ScopeJunction.com -- he replied: In some ways bandwidth is the least important parameter. For a 100 MHz clock rate, you need a bandwidth of at least 350 MHz. More important are things like triggering, sampling rate (for digital scopes), pulse capture, etc. It would take at least an hour to explain all of the factors involved. Look here http://www.tek.com/learning/oscilloscope-tutorial for tutorials.
"How does one know what oscilloscope bandwidth is required for a design? e.g. if MCU is 100MHz, what bandwidth of oscope is required? Is that the right question to ask?"
Re the mention of implementing a Cray on an FPGA -- you are right -- a Cray Supercomputer from I think the 1980s was recently replicated on a single (not so big) FPGA by a young designer -- check out thsi article: http://www.programmableplanet.com/author.asp?section_id=2340&doc_id=247408&
@Luizcosta: Re your question about natural language -- I'm not sure -- if we get to the point where th ecomputers knwo wha twe are saying, then we are at the point where they can design themselves -- check out my review of Robopocalypse by Daniel H. Wilson http://bit.ly/SW6A6j
FUN PROJECTS: I read some cool reports from folks who have implemented several CPUs such as Zilog Z80 and other processors using FPGA. Even a CRAY implementation can be found on the web.
Also "Hamster" in New Zealand just did a blog about the different FPGA boards he has -- check out thsi article: http://www.programmableplanet.com/author.asp?section_id=2340&doc_id=247935&
@MAX: Don't you see a time when discrete digital logic thinking will no longer be necessary, when all solution thoughts will be implemented by natural languages?
@Samdisp06: Re looking for an inexpensive FPGA dev kit. Duane on APP (AllProgrammablePlanet) is uasing an $89 one (search for "Discovering FPGAs") -- but Gadget Factory gave us a special offer on one known as a Papilio Board for about $35 -- check out this article: http://www.programmableplanet.com/author.asp?section_id=1925&doc_id=247412
@EdB_Vt: which Huntsville are you going to be in and when? And you have evidence that Max will also be in this same Huntsville sometime soon? Inquiring minds want to know....
@Vinaya: Again. I think you will find the discussions on AllProgrammablePlanet.com to be agood place to start ... do a search on "Ask Max" and "Ask Adam VHDL" and "Discovering FPGAs" (that will keep you busy for a while :-)
@Vinaya: I think FPGAs are a REALLY good area to get into. Before you learn FPGAs you need to understand basic digital concepts -- then you are going to have to learn a hardware programming language like Verilog of VHDL (which is the best is aon on-going debate)
2 Questions:1. Is there a hobbyist/experimenter/workbench kit for "playing" with these devices and the associated logic much like the Arduino or is there a better way to learn this? 2. What common items have Zynq-7000's or similar FPGA's in them? Thanks for these classes.
@shorek - without pull-up, line will float unless it's being pulled up or down by a logic gate. floating means you won't be able to predict what it is. pull-up makes it predictable value. (usually a '1' - then logic gate pulls the signal down to '0')
Yes, I think the point is that Max is combining early history so we can see how the technology grew, and now the devices are so complex that you can't assimilate it all in your mind. The goal is to have a general understanding of where we came from and how fast the technology grew, but to really design ASICs and FPGAs you will ned a LOT of VERY specialized training. This is just an intro...
@bmatts - changing a logic line from "0" to "1" requires a small bit of charge (electrons), changing from "1" to "0" requires that to be drained to ground. Mulitply this by a gazillion logic gates and gigaherz clock speeds results in significant current flow. High current flow results in heat generation.
You're right from a literal sense, of course. Otherwise the signal flow wouldn't allow for independent OR gates. The way it's drawn is obviously just to simplify the diagram.
@RudySchneider: I appreciate your comment. however, if you look closely to the boolean equations in all the examples, you'll realize that those vertical lines with the cross-connect on the vertical line, they imply a three wire connection to the output OR gates. By the way, SOP stands for Sum of Products like in the boolean equation w = a & B & C | A & B | A & C, which requires 3 input OR gates.
@MAX: It appear to me that, for the beginner, the output OR gates on the PLA diagrams should indicate that they have 3 inputs (to implement the SOP sythesis teqhnique).
(presuming Rich asked question about what we've done with programmable devices) haven't used FPGAs; interested in learning about them. have used some stuff long time ago
@RICH: As I asked before, what is the problem of coming live a few minutes before the hour as the other webinars do nowadays? That would be a huge adantage to the participants.
Rich - some of the webinars I have attended do have a "the webinar will begin in X minutes" message in the period 5-10 minutes preceeding the event. This is super handy to determine if one's system is up to th task. You may suggest it if you get the opportunity.
Otherwise - these continue to be great sessions. Thanks to Digi-Key, yourself, and Max
@Emily, I heard about the courses through a co-worker back in January. He possibly was on a design news mailing list. I thought, why not give it a try and see what the courses are all about. That was 14 courses ago.
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