Good presentations and a lot of information (and anecdotes) shared in these two courses. I hope any constructive criticism is for the betterment of future classes, for the enhancement and clarification, self documentation and completeness so that some good classes can be made better and archivable.
I imagine the Brown's ferry operators chose to begin a manual shutdown prior to conditions progressing to the point at which the Reactor Shutdown System actuated a SCRAM of the reactor which is a more severe transient on the reactor. Had conditions been such at the loss of the pumps that an anticipated event without scram occurred, that would have been a very bad situation and the world woud have been made aware of it.
My first thought for the void was containmen,t should the furnace fail and all the molton glass leaked out in a big spill, But then when that much glass hit that water in the bottom there would no doubt be one big explosion when the water "flashed" to steam. Anyway thanks for a very good lecture over the past two/three weeks.
I see a lot of growing interest in the use of OS in embedded systems. Let me recommend that you folks take a look at the Purdue prof. Dug Comer's project XINU. A great solution for OS base embedded solutions. It's being used unnanounced by many equipment manufactures. An excellend way to get a barebones kernel and develop extentions your self. XINU has now a virtual appliance so we cna learn to build OSs on a Virtual Box or implement it on a LynkSys router.
@Ran "Can you compare your FPGA explanation to that of SOC?"
Thonk of them as th esame in this context -- both could be used to implement hardware accelerators -- both can have processor cores and on-chip memory (the ASIC/SoC can have only a hard processotr core, the FPGA can have hard or soft) -- the extermal microcontroller sometimes hands control or data processing functions over to the ASIC/SoC or FPGA...
Another video -- This one starts with a real news report, then leads into two Australian comedians doing a spoof interview (lots of good lines, but the one I like is "I'm not a botanist") www.youtube.com/watch?v=W77IqQW9xzU
@"Max, have you heard of anyone putting an actual OS on a FPGA."
Yes -- absolutally -- for example you can run the Micrium RTOS uC/OS-II or OS-III on the 32-bit soft processors like Nios on Altera FPGAs or MicroBlaze on Xilinx FRGAs -- and you can run Linux on any sofy or hard core on an FPGA so long as it has an appropriate Memory Management Unit (MMU)
@Ran -- the usual thing is that you hav eth emicrocontroller executing regular code -- then it will pass some data to the FPGA -- tell th eFPGA to deal with uit -- the FPGA will perform humongous amount sof calculations very quickly (the microcontroller can carry on doing its own thing) and then th eFPGA is finished it hand the results back to the microcontroller
Tnaks Max, It was a real pleasure attending the past few weeks. It reminds me of my early military training when the most entertaining and effective instructors mixed "war stories" with the lesson material. That was back when some of them had first hand experiece on Lancasters for maritime patrol in the RCAF.
@danlafleur- My connection is doing it as well. Max is also getting lower every once in awhile, but I think that is just him pushing back from the microphone.
I had a eval board and play with it. there are OA and other comp in diff cells what you can conect them in diff ways as you do in fpga with your cells. there is also the s/w with it to be able to do that.
@Alex - Can you please clarify? I am confused. It was my understanding that next week there would NOT be a presentation. However, your "Curriculum Calendar" web page shows the track titled "System-Level Testing & Debugging" starting on Monday, March 19, which is 3 days from now - not 10 days from now. Where am I going wrong here?
@slk, there was a certain level of confidence when I could single step the code and look at the hardware and register values with a front panel console or debugger through a terminal. Freeze the program and probe the hardware for the trouble.
Alex, I agree. Back when I had to count cycle time for uP, I had a good feel for how the system worked. Now the cycle time is transparent until I have a timing issue.
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