The P.I.D. algorithm question's answer should note that PID filers are or should be made to be 'tunable'. It comes back to the issues of accuracy and precision (how close to the exact set point do you need to get and stay without oscillation for example). The startup problem like also 'special cases' is usually also addressed in all PID algorithms. Choosing a 'P' - proportional setting such as 50% which is halfway between the starting point (first measurement) and desired point (temperature, fill position etc.) implements a sort of 'binary search' to move closer to the set point. In seeking the set point, now the parameters for 'I' Integral which is a sort of running average, and 'D' Derivative which is the slope or rate of change can be determined. In addition, prior knowledge of the controllers and sensors and other elements in the control system help to determine values for PID set points. There are many good tutorials on PID and PID tuning online - enjoy!
Side note -- Labview has FPGA capabilities - see for example http://www.ni.com/fpga/ or do a web search as there are other specific white papers/app notes and information online in general and at National Instruments (NI's) website.
Someone said "Max, what is deiferences between Verilog HDL and FPGA?"
HDL stands for Hardware Description Language. Unlike programming languages like C and C+ (which are inherently sequential in nature), a HDL is designed to represent the way in which hardware works -- concurrentkly, which means that multiple things can be happening at the same time.
We use HDLs like Veriloh, VHDL, SystemVeriloh, or UDL/I (from Japan) to capture the intent of our design -- then we use logic synthesis to take this high-level representation and generate a gate-level equivalent.
ASICs and FPGAs are silicon chips -- we use the gate-level output from the systhesis tool to either (a) build a new ASIC or (b) program / configure an FPGA.... thsi is a simplistic description but I hope it helps
As a constructive criticism, it would be helpul toshow for each bullet, the talking points being discussed. Coming from a classical bkground, I'm trying to picture the ladder during the several minutes that the topic is being discussed... looking at only the highlighted topic. When we get to a meatty slide, Max says it is too complicated and moves on. Other times I'm staring at a pretty box for several minutes while the guts of the box is what I'm trying to picture. Also, I like my achronyms defined in print at least once. Sometimes the presentation appears at a very high level, good for the boardroom, less so for practitioners. Every sentence had an "ah". Having said all that, I'm grateful for the program. ggg
@syakovac, "virtual peripherals"! I like the idea of high speed hw and programmable configurations. A small example is a fairly fast uC Parallax SX chip and peripheral blocks defined in software. The uC can keep up quite well with normal applications.
Someone said "I'm still unclear as to why one would use FPGAs to emulate SoC when the SoC already exists in hardware"
I think it's more a case of when you are designing a new PLC or PAC or SBC for an industrial control application -- if there's already an exuisting SoC (ASIC / ASSP / whatever) that does everything you want then you woudl use it. But if the existing SoC doesn;t do what you want ... it will cost millions of dollars and at least 18 months to develop a new one -- or you can get an off-the-shelf FPGA and program it to do whatever you want it to do...
Just a request: if not tomorrow, then maybe in the Advanced course in a couple of weeks, could you run a case study from requirements to implementation and emphasize the design trades you made and the reasons for each, so we can get our arms around when to use a PAC, when a PLC is good enough, and when the added power of an FPGA or SBC justifies the increased complexity and risk?
@danlafleur -- I have wanted to make a uC/FPGA system with some flash storage capable of "loading" high powered peripherals from the storage. I think there could be some advantages to be had but I have not seen the project that wants it yet so I have not tried the experiement.
@Max: Would you be able to discuss any control system architecture - either a PLC, PAC or DCS. with actual connections ( Field devices-junction box, analog/digital marshalling cabinets, buses, controllers, HMI) ? Or upload any ref. materials ?
Someone said "Guess I'm resistant to new technology. I didn't think much of transistors in the 60's either!"
I know folks who grew up with vacuum tubes and couldn;t make the transition to transistors. And I know guys who designed digital logic with transistors but thought 74-series logic gate ICs were too confusing and wouldn;t switch...
@Island_Al Yes, I agree with you for low runners vs. high runners for volume. Large runners tend to like ASICS and dedicated hardware. FPGAs can be piecewise expensive but I am seeing them come down and Altera has even tried to make it so that you can "convert" to an ASIC with a different press of the large gree button.
@syakovac Makes sense in larger volume equipment, but I think more of runs of 5 to 10 units. Thanks for your explaination. Guess I'm resistant to new technology. I didn't think much of transistors in the 60's either!
Someone asked "Max, any thoughts on FPGA self-modifying code similar to uP/uC self-modigying code?"
Thsi is a very interesting area. Th eoriginal FPGAs could only be programmed in their entirity. Morte recently we have "partial reconfifuration" in which some parts of the FPGA keep on running while others are being reconfigured. When I was in Norway 2 weeks ago visiting th eUniversity of Oslo I saw some amazing things in this area. The problem this is a big topic in its own right -- way to complex to go into detail here (especiallc considering th efac tthat I am a two-fingered hunt-and-peck) typist
Someone asked "What is the difference between L2 Cache and L3 Cache?"
Well, 3 -2 = 1 (grin)
Actually it's all a matter of proiximity and size. The L1 cach is spall, extremely fast, and tightyly coupled to the processor core(s). Th eL2 cache is bigger, not quite as fast, and a bit father away. And if you have an L3 cache its even bigger and a bit slower and even father away...
I'm still unclear as to why one would use FPGAs to emulate SoC when the SoC already exists in hardware and one would simply add the program rather than define the SoC in the FPGA and then still have to add the program. What advantage am I missing here? Perhaps by adding the hardware accelerator to perform higher precision or fast math? It "seems" like one-off cost would climb rapidly using FPGAs.
@syakovac: a couple of reasons to choose the simpler options like PLC or PAC might be cost (make vs. buy decision) or certifications (a commercially available unit may already have needed certifications that might be costly and/or time-consuming to achieve with a proprietary design based in an FPGA or SBC).
Yes.. you see,..if you get hold of one microcontroller good..it can do everything.. adc, opamp, dac,..interrups, daqing... why another PLC.. We really need to know the advantage of PLC over other means.
I'm interested mainly in event-driven (discrete-event) systems and control and eventually in hybrid (time-driven and event-driven) systems and control. Could you recommend some engineering tools (similar to Matlab/Simulink for classical (continuous and discrete_time systems) - simulation and model-based design) for event_driven and hybrid systems which could also automatically generate code for certain processors (PLC, microcontrollers, microcprocessors, FPGA, etc.) or intermediate code (C, Ladder, FBD, etc. )? Thank you.
DCS and PLC have been around for a long time. I think DCS can be associated with process control (continuous and batch). PLC is more associated with machine control. It doesn't mean they don't cross domains.
@cook429667: I had perfect audio during the first course with Jon Titus back in January, then my organization blocked it before the second course started (without notice of course). There were no overt errors reported until I tried to access blogtalkradio.com directly from my browser. You may want to try that. Now I listen on my phone instead.
I remember seeing a video about a smart warehouse, where they had a "heat map" of the placement of the stored items. They were reorganized on the fly by usage, and you could see "hot" stuff wander to the outer sides.
Looking over my notes, I remebered that Quartus (Altera) has a very good interactive tutorail on FPGAs and how to use all of the controllers, including m-files and design consoles to build them in virtual mode, plus test equipment to view operation.
It's fascnating to watch how normal PLCs are configured in pairs for safety applications. In a complete process automation system which has both PLCs and DCS, PLC can be programmed to stop distibuted control system applications to stop a running plant (of course in emergency situations). PLCs sure are amazing.
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Thanks Chris, I had a look at the pdf. It's interesting and deserves more time. This reminds me of the movie War Games where WOPR tries all possible solutions for an acceptable outcome. (the only solution was not to play).
There were some questions yesterday about Genetic Algorithms and their practical applications. They can be used to solve very complex problems, but as Max described they will find a suitable solution but it might not be the absolute best.
Here is a link to an Altera website that includes a PDF describing a high level understanding for their fitting algorithms for their FPGAs. In it they describe how they use the GA Annealing for determining a best solution for routing an FPGA.
Festo's BionicKangaroo combines pneumatic and electrical drive technology, plus very precise controls and condition monitoring. Like a real kangaroo, the BionicKangaroo robot harvests the kinetic energy of each takeoff and immediately uses it to power the next jump.
Design News and Digi-Key presents: Creating & Testing Your First RTOS Application Using MQX, a crash course that will look at defining a project, selecting a target processor, blocking code, defining tasks, completing code, and debugging.
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