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Jack this was very good  

Thanks

Iron

Great presentation and very informative lecture. Thank you Jack

Iron

now, i have to take a sleep and i will continue day 3 class tomorrow...

thanks to digikey and design news for this class for us accumulating PDH Certificates...

goodnight and good morning to all you guys and our dearly sir jack and sir alex...

GREAT PRESENTATION Sir Jack...i do enjoyed listening the lesson and discussion answering the questions so far...

now, i am in slide 35 and finishing the day 2 class lesson...thanks sir jack for a wonderful presentation...

i am now on a very interesting lesson slide 20...

i am now on slide 19 of the lesson...

just downloaded the presentation slides and now i am starting with slide 2...

good evening sir jack! i will continue now with your lesson for day 2 class...

Thanks for clarifying that cache is considered non-deterministic.

 

Iron

HELLO FROM MELBOURNE AUSTRALIA

ELECTRICAL, INSTRUMENTATION & CONTROLS ENGINEER

JUST CATCHING UP

Thank you Jack and Alex, very nice presentation, good information too.

Iron

Thanks Jack and Alex.  I learn lots of concepts on multicore arena.

Great presentation understand some things bettter now.

Iron

Thank you for great seminar!

Perfect, lots of inside-out experience! 

Great presentation understand some things bettter now.

Iron

Yes, so many projects are done with the existing hardware and familiar software tools with no thought about speed and efficiency -- or whether the processes involved are parallel.

Gold

I loved the Feature Management slide -- and the part about giving management some options.

Gold

Good presentation!  Partitioning is a key design strategy.  IOP's (I/O Processors) are a common architectural implementation, perhaps not common enough.  Partitioning means ownership, ownership (presuming 'buy-in) means accountability, accountability means interest and dedication (not that it isn't there otherwise, but harder to maintain).  Partitioning makes for easier design and debug, supportability and future product enhancements.

 

All this presumes someone cares and there is something to care about.  I hope many are opting out of the widget, gadget and whatchamacallit industries and looking for serious socially responsible engineering opportunities.  My main concern is the power grid and how societally power is used (and mis-used) and the attendant problems that will come with it.  Portable applications notwithstanding, devices, including batteries need to be powered from somewhere ...

Thank you Jack and Alex for another great lecture.

Iron

I can't even imagine 192 processors running together!  How is the work divided?

Iron

How is it that we have created cache that is so much faster than storage memory, but we still cannot significantly increase the speed of storage memory?

Iron

They had the same sound problems today too, huh?

Iron
It's a fuzzy line between Firmware and Software. Firmware generally refers to the low level code in ROM that doesn't typically change, like your computer's BIOS. If the code resides in silicon, I call it firmware, so a small embedded system is all firmware, while a PC has elements of each.
Platinum

Is there any difference between Firmware and software ?

Iron

Thank you, Jack - great presentation.

Iron

Are their ways to detrmine which elements are parallelizable?

Iron

Are timing issues more prevalent within a multi-core device or in multiple single processors combined on a single PCB?

Iron

Many core computers are becomming more and more like super computers and we could be able to afford a super computer like a desktop in the near future.

Iron

I've heard that GPU's are more efficient at doing computational tasks that CPU's aren't designed to do.

Iron

Multicore design is getting easier and soon you can get code developed for multicore systems off the internet.

Iron

There are many differences between Firmware and Software and Jack mentioned most of them.

Iron

Thanks for claryfing the firmware and software difference

Iron

Great presentation, thanks!

Iron

Thanks for valuable infomation

Iron

Alex, PDF slides please, and add a "flipped slide" noise to the presenter's powerpoint, so we know when he flips.

manya, I would be more concerned about whether the board manufacturers correctly supply the USB bus in the circumstance you describe. It strikes me as an edge case that a manufacturer would forget about, and either not test against, or not even implement. That would not bode well for a product.

Thank you Jack and Alex

Iron

thanks all  it was a great lecture

Iron

Tenacious, I agree to a certain extent, thats why Ia minterested in negotiating with the host rather than blindly trying to source 900mA. The USB 2.0 spec specifies that the port will shutdown automatically if more than 500mA is requested unless the HID negotatiates.  USB 2.0 connectors are rated at 1500mA.

Iron

On the definition of firmware, I stand corrected, Jack. ;) Although, one might guess that my definition might be correct sometime in the future. :)

THANKS JACK.  I learnt lot of concepts on multicore arena. Bye for today.

Iron

manya, there are chips from just about every manufacturer that do USB out of the box. Try using the chip sorting tools from Digi-Key or Mouser to find cheap chips from your preferred manufacturer that include USB.

snandu, the 300 LOC is in a project setting.  That is important.  If you have time going to meetings, developing requirements and testing procedures, that is what Jack was meaning.  If you do a simpler project on your own, and all of the documentation goes in your head or is minimal, you can easily get higher than the 300 LOC per month.

Iron

what is the difference betwwen firmware and software.

Well, my definition is that firmware is software that runs on an embedded system. And since I wrote the dictionary (The Embedded Systems Dictionary) that stands!

Iron

manya, I think snandu is right... you want to limit yourself to 500 mA, even if it is theoretically possible to use 900 mA in some cases. No one is going to know whether their USB ports are on a hub or not.

tenacious techhunter from what you said they  are almost the same 

Iron

@Snandu13, USB 2.0 specification states 500mA - 900mA.

Iron

Jack whats the best way to implement USB connectivity in an embedded application using a PIC, Atmel, ARM, etc without using a RS232 converter, i.e. to negotatite faster data speed and negotatiate more current from the host (I undersatnd it is possible to obtain 900mA from the host). E.g USB Audio self powered speaker.

That's a huge topic. Check out Jan Axelson's books.

Iron

@Tenacious, all I have found upto now are FTDI chips, that do USB/RS232.

Iron

Productivity of 300 loc per person per month ( correct and working ) in embedded area appears too low  at current times.  or am I too ambitious?

 

Well, the numbers vary a lot, but this is over the entire life of the project, not just coding.

Iron

Here here! PDF slides! I insist!

Manya, I thought 500 mA is the maximum you can draw from a single host USB. !!

Iron

I am using Google docs to view the powerpoint slides and it looks like the translation process from native Microsoft format is a bit lacking.  Any way we could get PDF versions of the slide decks posted?

 

manya, there is probably an HID device driver for that. Just use a chip that does USB out of the box, build it as the standard device, and you should be fine.

Jack whats the best way to implement USB connectivity in an embedded application using a PIC, Atmel, ARM, etc without using a RS232 converter, i.e. to negotatite faster data speed and negotatiate more current from the host (I undersatnd it is possible to obtain 900mA from the host). E.g USB Audio self powered speaker.

Iron

snandu, that number is the lines of code that are absolutely correct, and never need to be corrected. If you ever correct that line of code again, your number for that month goes down.

Jack, from your discussion about partitioning and breaking projects into subsystems, the requirement definitions and for each subsystem becomes extremely important to make sure you have the interface between them defined well. 

Iron

kenstan, the difference is mostly where the code "lives"... if it is read from embedded flash or an eprom, it's firmware. If it is read from a disk or removable storage, then it's software. But frankly, there isn't much significant difference. One would presume that you want underlying system behavior to be in the firmware, but it doesn't have to be so.

Productivity of 300 loc per person per month ( correct and working ) in embedded area appears too low  at current times.  or am I too ambitious?

Iron

Great selection of complex topics as expected. Thanks a lot, Jack!

Iron

what is the difference betwwen firmware and software.

Iron

In multiple cpu embedded system, we need to write firmware for each cpu independently and interactively. Is my understanding correct, Jack?

Yes. And that means build times go way down, saving more time.

Iron

Jack lets say, a 3 axis CNC machine, three PIC 16F's are used to drive each of the motors and a 4th PIC is used to communicate between each driver board and the computer running the cad software. Would this be more effective than a single PIC doing all tasks.

That's a classic case for using all of the PICs. It's exactly like the assembly line. If cost isn't everything, I'd use the four parts.

Iron

The key then is from the design stage for the problem at hand; evaluate whether can be best handled serially or if there are intense processing which require minimal shared resources.

As shared resources for each section indicate very high cohesion, it is probably best to employ single controller architecture and cache.

I assume also that the timing of each potentially partitionable task will also be of concern to avoid bottlenecking.

Iron

In multiple cpu embedded system, we need to write firmware for each cpu independently and interactively. Is my understanding correct, Jack?

Iron

Jack lets say, a 3 axis CNC machine, three PIC 16F's are used to drive each of the motors and a 4th PIC is used to communicate between each driver board and the computer running the cad software. Would this be more effective than a single PIC doing all tasks.

Iron

Jack, any experience with multi-master I2C and multi-core?

 

No, though it introduces more complexity, I'm sure it could be done.

Iron

Jack, what happened to "bit slicing"? Anyone still pursuing that route?

 

Ah, the old AMD 2900 series! It faded aways as CPUs got faster.

Iron

Is there a good reference on the web (AKA free) for the cocomo method and how I might translate it to pertain to synthesizable digital design?

 

I'm sure there is. Barry Boehm was the guy who started it. But it's really tough to use in the real world as you have to calibrate so many constants to your outfit using empirical data.

Iron

Jack, any experience with multi-master I2C and multi-core?

Jack, what happened to "bit slicing"? Anyone still pursuing that route?

Iron

Is there a good reference on the web (AKA free) for the cocomo method and how I might translate it to pertain to synthesizable digital design?

Iron

jack what do  you have to say  about protues as a stimulation tool

 

Sorry, not familiar with it.

Iron

In an embedded system, would connecting multiple (say 2) PIC16F chips be more effective at running tasks than having a single larger PIC?

It all depends on the application. I wish I could make a general statement, but can't.

Iron

jack what do  you have to say  about protues as a stimulation tool

Iron

jack, anything coming down the pike that would put multi-core CPUs on a switched fabric instead of a system bus? In particular, I'd like to be able to do multiple simultaneous interrupts.

Look at ARM's AHB. It's pretty amazing.

Iron

For SPI/UART simulation, go to opencores.org and download one.  Most run pretty easily with Icarus Verilog

Iron

Jack, do you see a point in time when cheap memory will mean faster?


Speed tends to go up, but there are fundemental limits (gads, I sound like Newt!). It's hard to move data between chips quickly. So some, like Xilinix, are stacking dies using "interposers" that can support 10,000 connections at high speeds.

Iron

In an embedded system, would connecting multiple (say 2) PIC16F chips be more effective at running tasks than having a single larger PIC?

Iron

jack, anything coming down the pike that would put multi-core CPUs on a switched fabric instead of a system bus? In particular, I'd like to be able to do multiple simultaneous interrupts.

Jack, Which is the most comfortable  easy to use simulation software for five different communication interfaces ( UART and SPI )?

I've seen people do this with the Keil stuff. Also some folks actually build simulation hardware to toss real data around. It's so easy to do nowadays!

Iron

Jack, do you see a point in time when cheap memory will mean faster?

Iron

in the "Feature Management" theory (I forget who originally came up with this), the theory says "wild guesses" are based on past experience. they compare this to building a house or other common repetative projects. this too is a trap, because past experiences is most beneficial when you are building the same widget over and over. most software and hardware projects are something that has never been developed before. either you haven't developed it. and/or you are using new and different platform/tools etc.

Iron

I might point out that feature management (slide 14) could go one stop further and list future enhancements to later products in the series. This would mesh well with AMP, where the designer purposely allows a place for such enhancements to be "plugged in" to the design with modest effort. Also a good way to manage "scope creep."

Good point! Also, it's critical to have a change control procedure. Changes have cost/schedule implications, and to pretend otherwise dooms a project.

Iron

heh ... "scope creep" today means something totally different from yesterday's "creepy scopes" :-)

Iron

Jack, any suggestions on restoring determinism to the CPU while taking advantage of "improvements" like cache?

That's another Great Unknown. Cache is inherently non-deterministic.

Iron

Jack, Which is the most comfortable  easy to use simulation software for five different communication interfaces ( UART and SPI )?

Iron

I might point out that feature management (slide 14) could go one stop further and list future enhancements to later products in the series. This would mesh well with AMP, where the designer purposely allows a place for such enhancements to be "plugged in" to the design with modest effort. Also a good way to manage "scope creep."

At ARM Techcon, there was a nice demonstration of an asymetric dual core, Cortex M4 and M0, part.  The M0 was used for all the I/O like isochronous USB audio leaving the M4 free to do all the audio processing without getting constantly interrupted to support the IO.

That's probably NXP's LPC4350. I have some here and have run some studies that show real advantages to this.

Iron

jack21, I work at Tektronix and we refer to FPGA code as firmware and sometimes even software. Part of the reason is that we have real hard-core analog engineers here. It took me a while to get used to this when I first started.

Iron

Jack, I asked this earlier: is anyone studiying system identification for cpu allocation?

Some RTOSes offer very sophisticated mechanisms to move tasks between CPUs depending on load. Or one can specify "task affinity," to keep a task on a particular CPU.

Iron

Jack, any suggestions on restoring determinism to the CPU while taking advantage of "improvements" like cache?

I was aware of the low productivity of meetings, Schmiedl, I just wanted some confirmation on how he was looking at productivity. Many people, myself NOT included, consider themselves better than 300 lines of code a month. :)

At ARM Techcon, there was a nice demonstration of an asymetric dual core, Cortex M4 and M0, part.  The M0 was used for all the I/O like isochronous USB audio leaving the M4 free to do all the audio processing without getting constantly interrupted to support the IO.

Jack, thank you, Can a GPU then be used to run normal tasks that would be done by a CPU?

 

There's a lot of work going on to study this. Some of the next-gen supercomputers will use GPUs.

Iron

@manya: theoretically yes, but what would the other 230 cores do in the meantime?

Iron

Has anyone considered AMP where the processors have different clock speeds?  My laptop has multi-processors which is great for rendering graphics and other processes.  But how fast does a processor have to run for word processing when what I'm really doing is typing.  Better to have a processor runnig very slowly (I don't type that fast.) and not executing a lot of wait instructions.  Slower clocks require less power, longer battery life, etc. as you point out.  Isn't having a fast processor asleep and a very slow processor running without a lot of wait cycles preferable to having several very fast processors running a huge number of no-op instruction waiting for me to type the next letter.

That's exactly the idea behind ARM's new big.LITTLE architecture.

Iron

Does the industry ever use "firmware" to describe FPGA, CPLD etc. code, (e.g. VHDL)?

I've heard it used that way. But there's no standard useage.

Iron

Jack, I asked this earlier: is anyone studiying system identification for cpu allocation?

Iron

Also, how do you go about making your "wild guesses"?

Iron

Jack, thank you, Can a GPU then be used to run normal tasks that would be done by a CPU?

Iron

Has anyone considered AMP where the processors have different clock speeds?  My laptop has multi-processors which is great for rendering graphics and other processes.  But how fast does a processor have to run for word processing when what I'm really doing is typing.  Better to have a processor runnig very slowly (I don't type that fast.) and not executing a lot of wait instructions.  Slower clocks require less power, longer battery life, etc. as you point out.  Isn't having a fast processor asleep and a very slow processor running without a lot of wait cycles preferable to having several very fast processors running a huge number of no-op instruction waiting for me to type the next letter.

Iron

Do you happen to know what the cocomo constants are for RTL design (Verilog)?

 

It hasn't been studied.

Iron

Homework assignment: go look up the kinds of memory inside a GPU :-)

Iron

Any recommended texts on parallel programing using multicore vs multi (independent) microcontrollers environments and inherent consideration of resource management strategies?

I don't know of any.

Iron

Do you happen to know what the cocomo constants are for RTL design (Verilog)?

Iron

the real world problem with using the "Feature Management" approach on slide 15, is that management holds you to these wild guesses. They do not understand and do not want to accept the concept of this approach, management are not normally engineers. and what makes matters worse, is that they are WILD guesses. when you actually get into the project, these initial estimates can change drastically, and note, you have already spent appreciable time on the effort. and then, as the effort progresses, there are obsticles you had no way of anticipating. just wanted to point that even though this seems like a very simple and seductive approach to project management, it is very difficult if not impossible to implement in an actual working environment.

Yep. But the only "solution" is complete honesty between them and us. In most companies that doesn't happen. I could go on about scheduling all day!

Iron

Thanks, Jack.  Very informative.

Jack, How does a GPU differ to a CPU?

 

A GPU is massively parallel collection of CPUs that are aimed at image processing.

Iron

@Tenacious Techhunter: IIRC, the numbers are taken across the complete project, i.e. they take into account the time you spent in meetings or writing docs, where you produce 0 LOC

Iron

Any recommended texts on parallel programing using multicore vs multi (independent) microcontrollers environments and inherent consideration of resource management strategies?

Iron

In embedded system , how do we decide the no of cpus optimally? Then each falsh has to be independently programmed. Am I right?

 

There's no algorithm to do this; it's all careful design and partitioning of the problem.

Iron

the real world problem with using the "Feature Management" approach on slide 15, is that management holds you to these wild guesses. They do not understand and do not want to accept the concept of this approach, management are not normally engineers. and what makes matters worse, is that they are WILD guesses. when you actually get into the project, these initial estimates can change drastically, and note, you have already spent appreciable time on the effort. and then, as the effort progresses, there are obsticles you had no way of anticipating. just wanted to point that even though this seems like a very simple and seductive approach to project management, it is very difficult if not impossible to implement in an actual working environment.

any thoughts on this?

Iron

Jack, How does a GPU differ to a CPU?

Iron

according to this definition of firmware even all the complex stacks (eg tcp ip) running on embedded processor are also firmware. Is it so?

This is one of those questions like the one Justice Stevens answered: I can't define pornography but I know it when I see it. Similar for embedded system and firmware. The line is fuzzy, but I'd call all ofhte code in an embedded system firmware.

Iron

tomfeliz, if it's not parallelizable, it's because there is a hardware limitation, and for no other reason. Two cores cannot access the system bus at the same time, for instance. Virtualization gets you nothing, in this circumstance. What matters is, is it parallelizable AT ALL? If it is, you don't need virtualization to solve it, though you may prefer that route, if it saves you writing code.

Does the industry ever use "firmware" to describe FPGA, CPLD etc. code, (e.g. VHDL)?

Iron

In embedded system , how do we decide the no of cpus optimally? Then each falsh has to be independently programmed. Am I right?

Iron

Jack, Does a beowulf cluster or blade server use ASMP, limited by the connectivity on the copper/fibre backplane? How would code be compiled to run on each blade/computer?

Mostly these datacenter-like applications use SMP, because these problems (like search) are naturally parallel.

Iron

Thanks Jack for the presentation.

Iron

So one can imagine that a programmer might do 500 lines of code in a month, thinking that he's better than 300 lines of code, but will only manage to get 300 lines of code correct, and have to rewrite 200?

according to this definition of firmware even all the complex stacks (eg tcp ip) running on embedded processor are also firmware. Is it so?

 

Iron

So another way to think of AMP can be understood with an example in the hardware world where one defines a mechanical or electrical interface, and all components are designed to meet that standard. Think the Common Berthing Mechanism on the space station. In AMP, that interface would be the serial comm with its electrical and protocol standards... And this interface offers the perfect point for testing. One can look toward the outside world and check the data coming in, or feed synthetic data toward the CPU

Tenacious, virtualization allows non-parallelizable tasks to be made parallel. The universe of parallel-friendly tasks is rather small, and it seems like other solutions are needed to exploit multicore for a lot of other problems. For instance, a single low-power Core 2 Duo CPU can run 3-4 VMs very efficiently in less than 20 Watts.

Iron

jack21: do you have any experience about using AMP with _large_ amounts of data? How does passing al those bits along compare to retrieving it from memory?

Sure. Large amounts of data problems are common in SMP when the data is very regular (think weather modeling), and in data comm, where AMP works really well. In data comm they often push tens of GB/sec.

Iron

Jack, Does a beowulf cluster or blade server use ASMP, limited by the connectivity on the copper/fibre backplane? How would code be compiled to run on each blade/computer?

Iron

jack21: do you have any experience about using AMP with _large_ amounts of data? How does passing al those bits along compare to retrieving it from memory?

Iron

Jack, earlier, you mentioned productivity on the order of 300 lines of code per month... Is that the number of lines of code that are absolutely correct and don't need to be rewritten, or simply raw code that might need to be rewritten?

That's completed, working code.

Iron

whats difference between firmware and bootloader?

Firmware is embedded code. A bootloader is firmware.

Iron

Jack, earlier, you mentioned productivity on the order of 300 lines of code per month... Is that the number of lines of code that are absolutely correct and don't need to be rewritten, or simply raw code that might need to be rewritten?

whats difference between firmware and bootloader?

Iron

COCOMO = Constructive Cost Model

Iron

There Are notes below the presentations, that explains fx cocomo..

Iron

Constructive Cost Model (COCOMO

 

You mentioned early in the presentation that functions should be limited to 50 LOC or less.  Where does this number come from, how was it determined?

50 LOC comes from the observation that we want it all on one page, so we can see the entire function.

Iron
Thank you for aninterestin presentation, particular the benefit of keeping things focused and manageable
Iron

Excellent presentation, thank you

Iron

tomfeliz, virtualization isn't going to solve whether something is parallelizable or not. It either is, or it isn't.

Someone asked about tools to make problems parallel - that has been The Great Quest for 30 years.

 

Iron

Thank you! Great presentation.

Iron

Jack,

You mentioned early in the presentation that functions should be limited to 50 LOC or less.  Where does this number come from, how was it determined?

Thanks Jack & Alex!

Iron

pic10f is sot-23 package

Iron

great presentation. you really have my mind running...

Thanks for simplifying the evolution of CPU/memory architecture.

Iron

cmeadows, because you aren't using the same type of chip, it is no longer symmetric.

PIC10F is that 6 pin MCU Jack alluded to...

Silver

Thanks for a very informative session.

Iron

tomfeliz - VMWare is working on that problem

Iron

yes, i've used multiple micros to replace hardware, now we can do this with multicore and virtual hardware.

Iron

Thank you Jack, great presentation.

Thank you Alex as well.

Iron

so bigger is not always better when it comes to smp design?

Jack, this is an excellent presentation. Complex issues in plain English isnt easy, and you did it. Excellent.

 

Iron

Wouldn't it make sense, in appropriate smaller embedded applications, to use multicore 8-bit CPUs rather than 16-bit or 32-bit multicore CPUs.  If yes, then are such "small" products available?  I would presume that most multicore offerings are targeted to the larger applications thereby leaving the small applications out in the cold.

Iron

Great session again, thank you!

What about virtualization in embedded systems? Seems like a great way to exploit multiple cores and better partition systems. It's also very energy efficient.

Iron

does arm with its different busses for memory, IO etc, minimize this problem?

thanks for a great lecture.  I have several of your books.  love them

 

Iron

thanks alex and jack. nice presentation.

thanks also to mdsmdsmd for posting the current slide #

Iron

I've used multiple PIC10F's to do just what Jack suggests and it has worked out VERY well.  Good advice! 

Silver

If we have multiple cpus, will the codes be independent and interactive? How do we handle the interface between the codes?

Iron

Thanks for your session today!

Iron

Thank you Jack and Alex. It was a good presentation. Great examples on SMP vs. ASMP and how this applies to embedded systems design.

Good stuff.  Thanks again.

Iron

Question: If memory slows down data why they keep making faster CPUs when we cannot take a real advantage of their speed?

Iron

Performance vs. Power Cost. In implementing a solution of separate single cores vs a multi-core setup, is there a power/heat penalty greater than implementing code into separated cores? Also, if product future is taken into account, how much reliability is there in a company to continue a multicore line vs. traditional single cores?

 

Iron

Jack, thank you for the lecture.

Iron

Thanks for another great lecture, Jack

Iron

Excellent!  Also, thanks for not interrupting him today, Alex. Much better. :)

 

What would be on our way to believe that the faster memories may one day be cheaper to develop than the slow ones like magnetic hard disks? If that were possible, than the bottleneckness of cache may go away, don't you think?

Iron

it appears to me that the bus traffic is the main problem.

 

Thanks for describing ASMP

Iron

I'm an old mechanical engineer who has gotten into microprocessore just a few years ago.  This course is showing me that I've got a lot to learn yet. Great presentation! Thanks.

Iron

Good presentation, thank you.

Interesting, thank you

Iron

thanks for  the lecture

Iron

Do you have any recomendations for tools to help parallelize applications?

 

Iron

I really like this presentation. Thank you .

Iron

Very Interesting Thank you.

Iron

Great Lecture, Thank you!

Iron

Great presentation. Thank You.

 

Iron

Thanks jack. Got sort of understanding..

Iron

kloc =

1000 lines of code

Iron

Kilo Lines Of Code

 

Iron

KLOC == thousand lines of code

Iron

KLOC = Thousands Lines of Code

 

Silver

Very interesting material! Thank you Jack and Alex.

Iron

Syakovac - thousand lines of code - KLOC

Iron

Thanks for the SMP vs AMP explanations

A ton of info to digest here.  Thanks, jack.

Iron

I was having computer problems at the beginning.  What does KLOC mean?

Iron

the extreme multicore scenarios that you describe - are they really applicable to embedded design? the problems are (usually) not that large... if you trying to solve really large problems with this approach - isn't it an indicator that you're trying to do something wrong?

Iron

******* SLIDE 36 ******** (Last Slide) **********

Iron

Thanks Jack, you are giving me responses to a problem I didn't expect to solve in this session!

Iron

******* SLIDE 35 ********

Iron

thats the way our eyes work also

******* SLIDE 34 ********

Iron

******* SLIDE 33 ********

Iron

Jack, as the multicore increases, don't we just need to use partition again, so we can divide and conquer?

Iron

******* SLIDE 32 ********

Iron

******* SLIDE 31 ********

Iron

******* SLIDE 30 ********

Iron

******* SLIDE 29 ********

Iron

******* SLIDE 28 ********

Iron

What are the factors to decide the size/type of memory that build with processor? Where/how to handle to inter-communocation/synchronization between multicores/processors?

 

Iron

******* SLIDE 27 ********

Iron

nice thing about multicore is virrtual hardware devices.

Iron

******* SLIDE 26 ********

Iron

******* SLIDE 25 ********

Iron

******* SLIDE 24 ********

Iron

******* SLIDE 23 ********

Iron

I guess I am late and wrong then!:)

Iron

Jack, all these CPU "improvements" make the CPU performance very non-deterministic. Any suggestions to restore determinism?

******* SLIDE 22 ********

Iron

Jack, is any body already using "systems identification" to allocate cpu allocation in multicore OS?

Iron

******* SLIDE 21 ********

Iron

******* SLIDE 20 ********

Iron

******* SLIDE 19 ********

Iron

Anyone ever see this movie (it says alot about similar to this conversation)

The First $20 Million Is Always the Hardest (2002) 

 

 

******* SLIDE 18 ********

Iron

having the system always "working" helps system verification tremendously, also.

Luiz, this estimation is the project manager's job.

and SW guys are usually wrong

 

Iron

LOL so true! HW guys are always late!!

******* SLIDE 17 ********

Iron

Jack, but "wild guesses" will be completely different depending on knowledge and experience. So, how do you hire peole who, in a large project, will be "wild guessers"? :o)

Iron

that's why concept and feasability stage is very important

Iron

Welcome to the scrum development methodology: a system that always works with increments of new functionality added in descending order of priority. It works great!

Iron

******* SLIDE 16 ********

Iron

While having multiple components / micocontrollers will help break down a large and complex project into smaller, and more manageable, pieces, the addition of more components also increases the complexity of the PCB layout, an additional components in the JTAG scan chain, additional configuration management of the firmware for multiple micro's, etc.  That being said, I still agree with this technique of adding additional "brain dead" processors for managing the project complexity.

 

Iron

But if you use the principles shown in the retro-encabulator, you'll be in good shape

Iron

******* SLIDE 15 ********

Iron

also an example of bad management

what about test of the radar before mounting on a tank or hooking it up to guns

 

Good, Fast, Cheap - Choose any two

Iron

fast, good, cheap. Choose two.

MultiProcessors: We must remember to handle synchronicity in many cases, i.e. shaft angle at this moment in time.

Iron

******* SLIDE 14 ********

Iron

adding more programmable components in a circuit means also more production time.

how do you address IPR issues with code reuse (code steal - in your slide 11)?

Iron

******* SLIDE 13 ********

Iron

do you mean is better to add additional component so as to reduce coding for the microcontroller

Iron

******* SLIDE 12 ********

Iron

******* SLIDE 11 ********

Iron

******* SLIDE 10 ********

Iron

ants do this well, take a huge job and break it down to small manageable tasks

Iron

But there are limits to that, particularly if both processors need to use the System Bus.

******* SLIDE 9 ********

Iron

So many electrical and software engineers try to inpress with complex code rather than impress with clean and robust functionallity and complete desriptions.

Iron

it's the KISS principle...

Iron

******* SLIDE 8 ********

Iron

OK, so now I'm viewing the slides on my work desktop PC and listening to the audio on my phone, so yes, it is clearly my company now blocking the audio. This is something new since the Basic MCU class a week and a half ago. I mention this since others may be able to use the same workaround.

Iron

Divide and Conquer? This is very good information, Jack.

 

Iron

******* SLIDE 7 ********

Iron

It would be interesting to see if there is any loss in productivity from partitioning code when using a multi-processor chip (aka Propeller) vs. multiple microcontrollers?

Iron

or label you varibles correctly

isum ?

@FrankBishop: No kidding! And the project management becomes an issue, also.

Audio is still weak. For tomorrow, maybe Jack can explore the microphone input settings. In most recent versions if Windows one can adjust the mic input level, and even over-drive it with some settings in the sound control panel.

Iron

someone knows how to interpret the graphs (@FrankBishop) ;)

Iron

I agree audio is worse today

Is this the number of lines of code that are correct and don't need to be rewritten, or are these lines of code that may also get rewritten?

Productivity really drops when you go from 1 developer to 

more than one

Still no audio, just like yesterday.

Iron

if there's no audio, it's cause your company is blocking live streams. The other thing to try is refreshing your browser but if that doesn't work, you're blocked.

Blogger

Try FireFox, you'll have no audio issues..

Iron

for audio try F5 (refresh your page)

Iron

Audio is fine here.

Iron

No audio here either. No widget to display audio controls.

Iron

His sound is just fine for me.

Iron

today audio sound is a little bit un-clear.

Iron

OK login again to quit audio loop, is OK now.

Iron

OK, audio is working well today.  Let's go!

 

Iron

audio is loud and clear (as usual)

Iron

does anyone else hear the audio intro looping?

Iron

We need the Powerpoint Slide switches to make a noise, that way we know when the presenter is switching slides. Also, why no PDF slides???

Has the audio started?

Iron

The human brain takes time to process as well.

Iron

looking forward to it... sounds really interesting

Iron

Ah another enjoyable 45minutes...

Iron

oh, BTW: why does nobody say RTOS for 1µs or RTOS for 1 ms? If I understand things correctly, _nothing_ can be guaranteed to be a RTOS for every interval. So RTOS only makes sense with a qualifie

Most RTOSes let you set the time base - the tic interrupt rate. 1 usec is too fast as the context switch time will swamp the CPU. Typ numbers are s few hundred usec to 10 msec or so.

Iron

could we say "near real time" or "close enough for the application"? for RTOS

Iron

oh, BTW: why does nobody say RTOS for 1µs or RTOS for 1 ms? If I understand things correctly, _nothing_ can be guaranteed to be a RTOS for every interval. So RTOS only makes sense with a qualifier.

Iron

use a semaphore, mutex or an ecb/queue construct

Iron

jack21: Still, in between the time where I see that in_use is free, and the time I get to setting it, another task could step in and take the resource away. If, in an RTOS, there are other tasks running.

You're right! And that's really the point of the slide. This is bad code that looks seductively correct.

Iron

jack21: Still, in between the time where I see that in_use is free, and the time I get to setting it, another task could step in and take the resource away. If, in an RTOS, there are other tasks running.

Iron

Jack, I've been reading your articles for years. It's an honor to be in this seminar with you.

Iron

hello all, ready for a great session.

Iron

how do you wait for a resource to become free again? I understand the handshake problem on slide 13, but I can't see a way around it right now. Or is the answer going to be "don't wait, have somebody tell you?

This is a multitasking system, so some other task is executing concurrently, and will drop the in_use flag.


Iron

cnorton, as long as youre on this page, you're logged in and should get credit.

Blogger

If you try and login and already are, it tells you that you are already logged in.

Iron

Alex,

While there is a moment before the session, there is a login button under the DesignNews banner just where the red line starts to curve upwards, one in the middle of the gray background Digi-Key banner just below that, and one in the Digi-Key continuing education box to the right of the "Post" box.  Which login should I be using to get credit for attending?  I'm never sure which.  Does using any of them work for showing that I am attending the session?

Iron

Be sure to click 'Today's Slide Deck' under Special Educational Materials above right to download the PowerPoint for today's session.

Blogger

The streaming audio player will appear on this web page when the show starts at 2pm eastern today. Note however that some companies block live audio streams. If when the show starts you don't hear any audio, try refreshing your browser.

Blogger

@jack21: I missed the answer to one of my questions from yesterday's session:
how do you wait for a resource to become free again? I understand the handshake problem on slide 13, but I can't see a way around it right now. Or is the answer going to be "don't wait, have somebody tell you?"

Iron

It also has a link above and to the right of the Login to participate link next to the facebook and twitter logos - if you are not logged in, it will say login.  If you are logged in, it will say logout.

Iron

Sorry for the post, just checking as website tells me to login to participate and I already have, so I wanted to confirm.

Iron


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