Yes, so many projects are done with the existing hardware and familiar software tools with no thought about speed and efficiency -- or whether the processes involved are parallel.
Good presentation! Partitioning is a key design strategy. IOP's (I/O Processors) are a common architectural implementation, perhaps not common enough. Partitioning means ownership, ownership (presuming 'buy-in) means accountability, accountability means interest and dedication (not that it isn't there otherwise, but harder to maintain). Partitioning makes for easier design and debug, supportability and future product enhancements.
All this presumes someone cares and there is something to care about. I hope many are opting out of the widget, gadget and whatchamacallit industries and looking for serious socially responsible engineering opportunities. My main concern is the power grid and how societally power is used (and mis-used) and the attendant problems that will come with it. Portable applications notwithstanding, devices, including batteries need to be powered from somewhere ...
How is it that we have created cache that is so much faster than storage memory, but we still cannot significantly increase the speed of storage memory?
It's a fuzzy line between Firmware and Software. Firmware generally refers to the low level code in ROM that doesn't typically change, like your computer's BIOS. If the code resides in silicon, I call it firmware, so a small embedded system is all firmware, while a PC has elements of each.
Many core computers are becomming more and more like super computers and we could be able to afford a super computer like a desktop in the near future.
manya, I would be more concerned about whether the board manufacturers correctly supply the USB bus in the circumstance you describe. It strikes me as an edge case that a manufacturer would forget about, and either not test against, or not even implement. That would not bode well for a product.
Tenacious, I agree to a certain extent, thats why Ia minterested in negotiating with the host rather than blindly trying to source 900mA. The USB 2.0 spec specifies that the port will shutdown automatically if more than 500mA is requested unless the HID negotatiates. USB 2.0 connectors are rated at 1500mA.
manya, there are chips from just about every manufacturer that do USB out of the box. Try using the chip sorting tools from Digi-Key or Mouser to find cheap chips from your preferred manufacturer that include USB.
snandu, the 300 LOC is in a project setting. That is important. If you have time going to meetings, developing requirements and testing procedures, that is what Jack was meaning. If you do a simpler project on your own, and all of the documentation goes in your head or is minimal, you can easily get higher than the 300 LOC per month.
what is the difference betwwen firmware and software.
Well, my definition is that firmware is software that runs on an embedded system. And since I wrote the dictionary (The Embedded Systems Dictionary) that stands!
manya, I think snandu is right... you want to limit yourself to 500 mA, even if it is theoretically possible to use 900 mA in some cases. No one is going to know whether their USB ports are on a hub or not.
Jack whats the best way to implement USB connectivity in an embedded application using a PIC, Atmel, ARM, etc without using a RS232 converter, i.e. to negotatite faster data speed and negotatiate more current from the host (I undersatnd it is possible to obtain 900mA from the host). E.g USB Audio self powered speaker.
That's a huge topic. Check out Jan Axelson's books.
I am using Google docs to view the powerpoint slides and it looks like the translation process from native Microsoft format is a bit lacking. Any way we could get PDF versions of the slide decks posted?
manya, there is probably an HID device driver for that. Just use a chip that does USB out of the box, build it as the standard device, and you should be fine.
Jack whats the best way to implement USB connectivity in an embedded application using a PIC, Atmel, ARM, etc without using a RS232 converter, i.e. to negotatite faster data speed and negotatiate more current from the host (I undersatnd it is possible to obtain 900mA from the host). E.g USB Audio self powered speaker.
snandu, that number is the lines of code that are absolutely correct, and never need to be corrected. If you ever correct that line of code again, your number for that month goes down.
Jack, from your discussion about partitioning and breaking projects into subsystems, the requirement definitions and for each subsystem becomes extremely important to make sure you have the interface between them defined well.
kenstan, the difference is mostly where the code "lives"... if it is read from embedded flash or an eprom, it's firmware. If it is read from a disk or removable storage, then it's software. But frankly, there isn't much significant difference. One would presume that you want underlying system behavior to be in the firmware, but it doesn't have to be so.
Jack lets say, a 3 axis CNC machine, three PIC 16F's are used to drive each of the motors and a 4th PIC is used to communicate between each driver board and the computer running the cad software. Would this be more effective than a single PIC doing all tasks.
That's a classic case for using all of the PICs. It's exactly like the assembly line. If cost isn't everything, I'd use the four parts.
The key then is from the design stage for the problem at hand; evaluate whether can be best handled serially or if there are intense processing which require minimal shared resources.
As shared resources for each section indicate very high cohesion, it is probably best to employ single controller architecture and cache.
I assume also that the timing of each potentially partitionable task will also be of concern to avoid bottlenecking.
Jack lets say, a 3 axis CNC machine, three PIC 16F's are used to drive each of the motors and a 4th PIC is used to communicate between each driver board and the computer running the cad software. Would this be more effective than a single PIC doing all tasks.
Is there a good reference on the web (AKA free) for the cocomo method and how I might translate it to pertain to synthesizable digital design?
I'm sure there is. Barry Boehm was the guy who started it. But it's really tough to use in the real world as you have to calibrate so many constants to your outfit using empirical data.
jack, anything coming down the pike that would put multi-core CPUs on a switched fabric instead of a system bus? In particular, I'd like to be able to do multiple simultaneous interrupts.
Jack, do you see a point in time when cheap memory will mean faster?
Speed tends to go up, but there are fundemental limits (gads, I sound like Newt!). It's hard to move data between chips quickly. So some, like Xilinix, are stacking dies using "interposers" that can support 10,000 connections at high speeds.
jack, anything coming down the pike that would put multi-core CPUs on a switched fabric instead of a system bus? In particular, I'd like to be able to do multiple simultaneous interrupts.
Jack, Which is the most comfortable easy to use simulation software for five different communication interfaces ( UART and SPI )?
I've seen people do this with the Keil stuff. Also some folks actually build simulation hardware to toss real data around. It's so easy to do nowadays!
in the "Feature Management" theory (I forget who originally came up with this), the theory says "wild guesses" are based on past experience. they compare this to building a house or other common repetative projects. this too is a trap, because past experiences is most beneficial when you are building the same widget over and over. most software and hardware projects are something that has never been developed before. either you haven't developed it. and/or you are using new and different platform/tools etc.
I might point out that feature management (slide 14) could go one stop further and list future enhancements to later products in the series. This would mesh well with AMP, where the designer purposely allows a place for such enhancements to be "plugged in" to the design with modest effort. Also a good way to manage "scope creep."
Good point! Also, it's critical to have a change control procedure. Changes have cost/schedule implications, and to pretend otherwise dooms a project.
I might point out that feature management (slide 14) could go one stop further and list future enhancements to later products in the series. This would mesh well with AMP, where the designer purposely allows a place for such enhancements to be "plugged in" to the design with modest effort. Also a good way to manage "scope creep."
At ARM Techcon, there was a nice demonstration of an asymetric dual core, Cortex M4 and M0, part. The M0 was used for all the I/O like isochronous USB audio leaving the M4 free to do all the audio processing without getting constantly interrupted to support the IO.
That's probably NXP's LPC4350. I have some here and have run some studies that show real advantages to this.
jack21, I work at Tektronix and we refer to FPGA code as firmware and sometimes even software. Part of the reason is that we have real hard-core analog engineers here. It took me a while to get used to this when I first started.
Jack, I asked this earlier: is anyone studiying system identification for cpu allocation?
Some RTOSes offer very sophisticated mechanisms to move tasks between CPUs depending on load. Or one can specify "task affinity," to keep a task on a particular CPU.
I was aware of the low productivity of meetings, Schmiedl, I just wanted some confirmation on how he was looking at productivity. Many people, myself NOT included, consider themselves better than 300 lines of code a month. :)
At ARM Techcon, there was a nice demonstration of an asymetric dual core, Cortex M4 and M0, part. The M0 was used for all the I/O like isochronous USB audio leaving the M4 free to do all the audio processing without getting constantly interrupted to support the IO.
Has anyone considered AMP where the processors have different clock speeds? My laptop has multi-processors which is great for rendering graphics and other processes. But how fast does a processor have to run for word processing when what I'm really doing is typing. Better to have a processor runnig very slowly (I don't type that fast.) and not executing a lot of wait instructions. Slower clocks require less power, longer battery life, etc. as you point out. Isn't having a fast processor asleep and a very slow processor running without a lot of wait cycles preferable to having several very fast processors running a huge number of no-op instruction waiting for me to type the next letter.
That's exactly the idea behind ARM's new big.LITTLE architecture.
Has anyone considered AMP where the processors have different clock speeds? My laptop has multi-processors which is great for rendering graphics and other processes. But how fast does a processor have to run for word processing when what I'm really doing is typing. Better to have a processor runnig very slowly (I don't type that fast.) and not executing a lot of wait instructions. Slower clocks require less power, longer battery life, etc. as you point out. Isn't having a fast processor asleep and a very slow processor running without a lot of wait cycles preferable to having several very fast processors running a huge number of no-op instruction waiting for me to type the next letter.
Any recommended texts on parallel programing using multicore vs multi (independent) microcontrollers environments and inherent consideration of resource management strategies?
the real world problem with using the "Feature Management" approach on slide 15, is that management holds you to these wild guesses. They do not understand and do not want to accept the concept of this approach, management are not normally engineers. and what makes matters worse, is that they are WILD guesses. when you actually get into the project, these initial estimates can change drastically, and note, you have already spent appreciable time on the effort. and then, as the effort progresses, there are obsticles you had no way of anticipating. just wanted to point that even though this seems like a very simple and seductive approach to project management, it is very difficult if not impossible to implement in an actual working environment.
Yep. But the only "solution" is complete honesty between them and us. In most companies that doesn't happen. I could go on about scheduling all day!
@Tenacious Techhunter: IIRC, the numbers are taken across the complete project, i.e. they take into account the time you spent in meetings or writing docs, where you produce 0 LOC
Any recommended texts on parallel programing using multicore vs multi (independent) microcontrollers environments and inherent consideration of resource management strategies?
the real world problem with using the "Feature Management" approach on slide 15, is that management holds you to these wild guesses. They do not understand and do not want to accept the concept of this approach, management are not normally engineers. and what makes matters worse, is that they are WILD guesses. when you actually get into the project, these initial estimates can change drastically, and note, you have already spent appreciable time on the effort. and then, as the effort progresses, there are obsticles you had no way of anticipating. just wanted to point that even though this seems like a very simple and seductive approach to project management, it is very difficult if not impossible to implement in an actual working environment.
according to this definition of firmware even all the complex stacks (eg tcp ip) running on embedded processor are also firmware. Is it so?
This is one of those questions like the one Justice Stevens answered: I can't define pornography but I know it when I see it. Similar for embedded system and firmware. The line is fuzzy, but I'd call all ofhte code in an embedded system firmware.
tomfeliz, if it's not parallelizable, it's because there is a hardware limitation, and for no other reason. Two cores cannot access the system bus at the same time, for instance. Virtualization gets you nothing, in this circumstance. What matters is, is it parallelizable AT ALL? If it is, you don't need virtualization to solve it, though you may prefer that route, if it saves you writing code.
Jack, Does a beowulf cluster or blade server use ASMP, limited by the connectivity on the copper/fibre backplane? How would code be compiled to run on each blade/computer?
Mostly these datacenter-like applications use SMP, because these problems (like search) are naturally parallel.
So one can imagine that a programmer might do 500 lines of code in a month, thinking that he's better than 300 lines of code, but will only manage to get 300 lines of code correct, and have to rewrite 200?
So another way to think of AMP can be understood with an example in the hardware world where one defines a mechanical or electrical interface, and all components are designed to meet that standard. Think the Common Berthing Mechanism on the space station. In AMP, that interface would be the serial comm with its electrical and protocol standards... And this interface offers the perfect point for testing. One can look toward the outside world and check the data coming in, or feed synthetic data toward the CPU
Tenacious, virtualization allows non-parallelizable tasks to be made parallel. The universe of parallel-friendly tasks is rather small, and it seems like other solutions are needed to exploit multicore for a lot of other problems. For instance, a single low-power Core 2 Duo CPU can run 3-4 VMs very efficiently in less than 20 Watts.
jack21: do you have any experience about using AMP with _large_ amounts of data? How does passing al those bits along compare to retrieving it from memory?
Sure. Large amounts of data problems are common in SMP when the data is very regular (think weather modeling), and in data comm, where AMP works really well. In data comm they often push tens of GB/sec.
Jack, Does a beowulf cluster or blade server use ASMP, limited by the connectivity on the copper/fibre backplane? How would code be compiled to run on each blade/computer?
jack21: do you have any experience about using AMP with _large_ amounts of data? How does passing al those bits along compare to retrieving it from memory?
Jack, earlier, you mentioned productivity on the order of 300 lines of code per month... Is that the number of lines of code that are absolutely correct and don't need to be rewritten, or simply raw code that might need to be rewritten?
Jack, earlier, you mentioned productivity on the order of 300 lines of code per month... Is that the number of lines of code that are absolutely correct and don't need to be rewritten, or simply raw code that might need to be rewritten?
Wouldn't it make sense, in appropriate smaller embedded applications, to use multicore 8-bit CPUs rather than 16-bit or 32-bit multicore CPUs. If yes, then are such "small" products available? I would presume that most multicore offerings are targeted to the larger applications thereby leaving the small applications out in the cold.
What about virtualization in embedded systems? Seems like a great way to exploit multiple cores and better partition systems. It's also very energy efficient.
Performance vs. Power Cost. In implementing a solution of separate single cores vs a multi-core setup, is there a power/heat penalty greater than implementing code into separated cores? Also, if product future is taken into account, how much reliability is there in a company to continue a multicore line vs. traditional single cores?
What would be on our way to believe that the faster memories may one day be cheaper to develop than the slow ones like magnetic hard disks? If that were possible, than the bottleneckness of cache may go away, don't you think?
I'm an old mechanical engineer who has gotten into microprocessore just a few years ago. This course is showing me that I've got a lot to learn yet. Great presentation! Thanks.
the extreme multicore scenarios that you describe - are they really applicable to embedded design? the problems are (usually) not that large... if you trying to solve really large problems with this approach - isn't it an indicator that you're trying to do something wrong?
What are the factors to decide the size/type of memory that build with processor? Where/how to handle to inter-communocation/synchronization between multicores/processors?
Jack, but "wild guesses" will be completely different depending on knowledge and experience. So, how do you hire peole who, in a large project, will be "wild guessers"? :o)
Welcome to the scrum development methodology: a system that always works with increments of new functionality added in descending order of priority. It works great!
While having multiple components / micocontrollers will help break down a large and complex project into smaller, and more manageable, pieces, the addition of more components also increases the complexity of the PCB layout, an additional components in the JTAG scan chain, additional configuration management of the firmware for multiple micro's, etc. That being said, I still agree with this technique of adding additional "brain dead" processors for managing the project complexity.
So many electrical and software engineers try to inpress with complex code rather than impress with clean and robust functionallity and complete desriptions.
OK, so now I'm viewing the slides on my work desktop PC and listening to the audio on my phone, so yes, it is clearly my company now blocking the audio. This is something new since the Basic MCU class a week and a half ago. I mention this since others may be able to use the same workaround.
It would be interesting to see if there is any loss in productivity from partitioning code when using a multi-processor chip (aka Propeller) vs. multiple microcontrollers?
Audio is still weak. For tomorrow, maybe Jack can explore the microphone input settings. In most recent versions if Windows one can adjust the mic input level, and even over-drive it with some settings in the sound control panel.
if there's no audio, it's cause your company is blocking live streams. The other thing to try is refreshing your browser but if that doesn't work, you're blocked.
oh, BTW: why does nobody say RTOS for 1µs or RTOS for 1 ms? If I understand things correctly, _nothing_ can be guaranteed to be a RTOS for every interval. So RTOS only makes sense with a qualifie
Most RTOSes let you set the time base - the tic interrupt rate. 1 usec is too fast as the context switch time will swamp the CPU. Typ numbers are s few hundred usec to 10 msec or so.
oh, BTW: why does nobody say RTOS for 1µs or RTOS for 1 ms? If I understand things correctly, _nothing_ can be guaranteed to be a RTOS for every interval. So RTOS only makes sense with a qualifier.
jack21: Still, in between the time where I see that in_use is free, and the time I get to setting it, another task could step in and take the resource away. If, in an RTOS, there are other tasks running.
You're right! And that's really the point of the slide. This is bad code that looks seductively correct.
jack21: Still, in between the time where I see that in_use is free, and the time I get to setting it, another task could step in and take the resource away. If, in an RTOS, there are other tasks running.
how do you wait for a resource to become free again? I understand the handshake problem on slide 13, but I can't see a way around it right now. Or is the answer going to be "don't wait, have somebody tell you?
This is a multitasking system, so some other task is executing concurrently, and will drop the in_use flag.
While there is a moment before the session, there is a login button under the DesignNews banner just where the red line starts to curve upwards, one in the middle of the gray background Digi-Key banner just below that, and one in the Digi-Key continuing education box to the right of the "Post" box. Which login should I be using to get credit for attending? I'm never sure which. Does using any of them work for showing that I am attending the session?
The streaming audio player will appear on this web page when the show starts at 2pm eastern today. Note however that some companies block live audio streams. If when the show starts you don't hear any audio, try refreshing your browser.
@jack21: I missed the answer to one of my questions from yesterday's session: how do you wait for a resource to become free again? I understand the handshake problem on slide 13, but I can't see a way around it right now. Or is the answer going to be "don't wait, have somebody tell you?"
It also has a link above and to the right of the Login to participate link next to the facebook and twitter logos - if you are not logged in, it will say login. If you are logged in, it will say logout.
As energy efficiency becomes more and more a concern for makers of electronics devices, researchers are coming up with new ways to harvest energy from sound vibration, footsteps, and even electromagnetic fields in the air.
The government wants to study your brain, and DARPA wants to use similar information to give robots true autonomy beyond any artificial intelligence developed to date. Sound like science fiction? It's not.
From Dell / Intel® New Paradigms in Design Work Scott Hamilton, vertical market strategist for Dell Precision workstations, 5/2/2013 3
Early in my career, I worked as a draftsman and remember the days of drawing on vellum with numbered pencils and Mylar with plastic lead. This was a fun experience in the sense that I ...
I've been using workstations for more than 10 years and love finding ways to get more performance from my system. With demanding professional applications that require more power each ...
A lasting memory from my first job as an engineer in an auto assembly plant is standing on hard concrete at six in the morning, vending-machine coffee clutched in hand, listening to ...
A quick look into the merger of two powerhouse 3D printing OEMs and the new leader in rapid prototyping solutions, Stratasys. The industrial revolution is now led by 3D printing and engineers are given the opportunity to fully maximize their design capabilities, reduce their time-to-market and functionally test prototypes cheaper, faster and easier. Bruce Bradshaw, Director of Marketing in North America, will explore the large product offering and variety of materials that will help CAD designers articulate their product design with actual, physical prototypes. This broadcast will dive deep into technical information including application specific stories from real world customers and their experiences with 3D printing. 3D Printing is
To save this item to your list of favorite Design News content so you can find it later in your Profile page, click the "Save It" button next to the item.
If you found this interesting or useful, please use the links to the services below to share it with other readers. You will need a free account with each service to share an item via that service.
Tweet This
8 
