Ohm's Law on reset signals usually has something to do with signal impedance and stray ingress capacitance creating a lower impedance and thus over riding the pull-up current. Its often a good measure to buffer the long lines with a small cap to suppress the much smaller stray capacitance.. I used to get stray resets when my lab of many computers was located in a carpetted unused office space. Here the ingress signal was many KV of ESD from a stray engineer opening the metal cage door to the lab. Zap,,,, the fix was a cheap can of anti-static carpet spray every week or two and making the sure the cage was not grounded so that impedance could be high and thus reduce the dv/dt rate, if when high static charges were created. Slowing down the discharge rate with 1 Mohm bleed resistor helps reduce the induced voltage more than grounding the conducting metal cage.
Both solutions worked independantly and even better together. It's just a simple application of Ohm's law for leakage and static discharge time constant.
This underlies the need for automated test development and regression at all levels. From formal design verification to post silicon or board diagnostics, each aimed at various aspects of fault detection from design aspects thru manufacturing processes. These days even small changes can and do have very complicated and likely poorly understood consqueces.
Many companies, especially smaller one's, still have little or no program to empass this ever growing need. Even in one's that do, many times, the value of the diagnosic developer is poorly understood or under appreciated. Only when bugs are found are you valued. When no bugs are found, you are viewed as overhead.
As someone that has ben in this role at large companies from pre- silicon all the way down to board manufacturing for over a dozen years, I can attest to the above.
Little by little, the need for such comprehensive stragies is gaining traction, and is most prevalent in the chip industry. As illustrated by the article, many times, the mfr gets away without performing an regressions for years, and then a problem pops up out of no where. A problem such as this is more expensive than ever. And no cost is higher than the potential loss of confidence by the customer or the impact on normal schedules (is there any such thing???) when the kind of interrupt that a situation such as this generates when it raises its ugly head???
These issues are always tough to troubleshoot without a good investment of time. Kudos on finding it!
I know that these issues can still occur, even with stringent DRC and multiple "Live Eye" checks, and it makes testing new devices troublesome at best for us. Is it the board, or the device? Also a lot of "green" layout designers aren't always up to snuff with doing the "Live Eye" check as they design or layout a design, and instead rely only on the DRC that the layout software provides. It is an area that I wish was focused on more in training.
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