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WarrenM
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Re: DAY3: CORTEX-M0 Structure, Discussion 2
WarrenM   8/22/2012 2:39:00 PM
NO RATINGS
Still interested in why Interrupt latency is 12 cycles. Is it basically the number of cycles the state frame needs to be saved, plus the Interrupt Vector fetch? There are 13 General Purpose Registers. Don't they all need to be saved? Wouldn't that be at least 13 cycles?



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