Someone said "Max, what is deiferences between Verilog HDL and FPGA?"
HDL stands for Hardware Description Language. Unlike programming languages like C and C+ (which are inherently sequential in nature), a HDL is designed to represent the way in which hardware works -- concurrentkly, which means that multiple things can be happening at the same time.
We use HDLs like Veriloh, VHDL, SystemVeriloh, or UDL/I (from Japan) to capture the intent of our design -- then we use logic synthesis to take this high-level representation and generate a gate-level equivalent.
ASICs and FPGAs are silicon chips -- we use the gate-level output from the systhesis tool to either (a) build a new ASIC or (b) program / configure an FPGA.... thsi is a simplistic description but I hope it helps
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