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Max Maxfield
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Re: Part II: Control System Feedback Loops
Max Maxfield   2/28/2012 3:01:06 PM
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@JM When would you consider an FPGA to be hardware vs. software?

That's such a tricky one -- let's make sure we all understand how thsi usually goes. You start with RTL like Verilog or VHDL that describes a hardware function -- then you use synthesis to conver tthsi into a gate-level netlist that gets loaded into the FPGA. The thing is that you roriginal RTL can include the code that describes a soft processor core, which you can then us eto execure conventional programs... so you tell me ... where do we draw the line?




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