Thermal Bandits Beget Shrinking Chip Packages

By: 
September 09, 2011

Every time we hear of a semiconductor company making a breakthrough in package size through some form of 3D transistor, 3D wafer stacking, or flip-chip packaging, the primary driver is assumed to be the battery-operated consumer device, particularly the smartphone. After all, what else can demand the most processing power with the least possible power consumption?

Yet there's another type of device that actually consumes as much power, if not more. It's the communications processors which support the burgeoning cloud datacenters. These are the thousand-server-plus warehouses that support Amazon, Facebook, and other online behemoths.

The network managers in charge of getting bits in and out of these datacenters demand dozens of ports, operating at 10Gbits/sec per port. They're already aggregating services in an area that today is as small as a PCI Express card. That soon may shrink to a mezzanine board the size of a credit card.

If you've touched the surface of a physical-layer chip used in 10Gbit Ethernet in recent years, you'll probably insist that putting a dozen such ports in an area of a few square inches simply is not possible. One such interface could fry an egg on a circuit board, were it not for miniature fans and heat sinks that help remove system heat.

If that's how you envision the problem, you haven't been paying attention to breakthroughs in package development for advanced chips, or similar advances in modules that tie processors to fibers. You also may be unaware that when a datacenter operator talks of 40Gbits or 100Gbits, it really means the aggregation (even within one chip) of multiple lanes operating at 10Gbits or at most 25. In short, all the years of work getting 10Gbit Ethernet established actually helped pave the way for faster future services.

To start, we can turn to the 3D wafer stacking that occupies the talents of big mixed-signal specialists like Texas Instruments Inc ., as well as the developers of million-gate FPGAs, like Xilinx Inc .

Sure, the new packaging techniques help standard systems in the IT and consumer video worlds, but communication interfaces remain a primary driver. Xilinx and its nearest competitor, Altera, spent years making sure that each interface to a large FPGA chip could operate at up to 28Gbits/sec, but they couldn't dissipate the heat generated if they didn't move away from traditional packaging.

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