Current-carrying capacity and temperature rise
How much current can a copper circuit safely carry? This is a question often voiced by designers who wish to incorporate heavy copper circuits into their project. This question is usually answered with another question: How much heat rise can your project withstand? This is because heat rise and current flow go hand in hand. Let's try to answer both of these questions together.
When current flows along a trace, there is an I2R (power loss) that results in localized heating. The trace cools by conduction (into neighboring materials) and convection (into the environment). Therefore, to find the maximum current a trace can safely carry, we must find a way to estimate the heat rise associated with the applied current. An ideal situation would be to reach a stable operating temperature where the rate of heating equals the rate of cooling. Fortunately, we have an IPC formula we can use to model this event.
IPC-2221A, calculation for current capacity of an external track :
I = .048 * DT(.44) * (W * Th)(.725)
The 2oz features connect control circuits, while 20oz features carry high current loads.
In this formula, I is current (amps), DT is temperature rise (C), W is width of the trace (mil), and Th is thickness of the trace (mil). Internal traces should be derated by 50 percent (estimate) for the same degree of heating. Using the IPC formula, we generated a chart showing the current-carrying capacity of several traces of differing cross-sectional areas with a 30C temperature rise. What constitutes an acceptable amount of heat rise will differ from project to project. Most circuit board dielectric materials can withstand temperatures of 100C above ambient, although this amount of temperature change would be unacceptable in most situations.
Circuit board strength and survivability
Circuit board manufacturers and designers can choose from a variety of dielectric materials, from standard FR4 (operating temperature 130C) to high-temperature polyimide (operating temperature 250C). A high-temperature or extreme environment situation may call for an exotic material, but if the circuit traces and plated vias are the standard 1oz/ft2, will they survive the extreme conditions?
The circuit board industry has developed a test method for determining the thermal integrity of a finished circuit product. Thermal strains come from various board fabrication, assembly, and repair processes, where the differences between the coefficient of thermal expansion (CTE) of Cu and the PWB laminate provide the driving force for crack nucleation and growth to failure of the circuit. Thermal cycle testing (TCT) checks for an increase in resistance of a circuit as it undergoes air-to-air thermal cycling from 25C to 260C.
An increase in resistance indicates a breakdown in electrical integrity via cracks in the copper circuit. A standard coupon design for this test utilizes a chain of 32 plated through holes, which has long been considered to be the weakest point in a circuit when subjected to thermal stress.
Thermal cycle studies done on standard FR4 boards with 0.8mil to 1.2mil copper plating have shown that 32 percent of circuits fail after eight cycles (a 20 percent increase in resistance is considered a failure). Thermal cycle studies done on exotic materials show significant improvements to this failure rate (3 percent after eight cycles for Cyanate Ester), but they are prohibitively expensive (five to 10 times material cost) and difficult to process. An average surface-mount technology assembly sees a minimum of four thermal cycles before shipment, and it could see an additional two thermal cycles for each component repair.
It's not unreasonable for a SMOBC board that has gone through a repair and replacement cycle to reach nine or 10 thermal cycles. The TCT results clearly show that the failure rate, no matter what the board material, can become unacceptable. Printed circuit board manufacturers know that copper electroplating isn't an exact science -- changes in current densities across a board and through numerous hole/via sizes result in copper thickness variations of up to 25 percent or more. Most areas of thin copper are on plated hole walls -- the TCT results clearly show this to be the case.
Heavy copper circuits would reduce or eliminate these failures. Plating of 2oz/ft2 of copper to a hole wall reduces the failure rate to almost zero (TCT results show a 0.57 percent failure rate after eight cycles for standard FR4 with a minimum of 2.5mil copper plating). In effect, the copper circuit becomes impervious to the mechanical stresses placed on it by the thermal cycling.