Embedded systems are at the heart of all our electronics today. Using microcontrollers, microprocessors, or digital signal processors, they are driving a rapidly changing modern technology. While some embedded systems can get by using only a small processor with little memory, some systems require extra computing power and external peripherals. It is not at all uncommon to see embedded applications that require entire operating systems. This is where system-on-chip (SoC) and system-in-package (SiP) designs can prove to be optimal choices. Typical SoC designs can consist of the processor, external memory, a timing source, analog-to-digital converters, and communication interfaces such as USB, UART, SPI, or I2C.
Due to the increasing complexity of modern designs, debugging these systems can sometimes turn out to be extremely troublesome. Some bugs can lay hidden in systems until it is too late -- when the product is already past its deadline and entering the production phase. The traditional debugging method involves hours of testing, which is never the most reliable route. Many companies are beginning to invest in software automation to handle much of their testing. This process can be more efficient and reliable, and has an increased chance of finding those hidden bugs.
Mentor Graphics' patented Questa Platform allows high-performance simulation in systems that integrate devices such as FPGAs and SoCs. As a result, companies can achieve more efficient design and verification management.
Mentor Graphics has just announced that it will be releasing an intelligent-software-driven verification (iSDV) feature to their Questa Platform. The iSDV will allow designers to generate C programs automatically that can run on multicore SoC systems. This allows companies to uncover more bugs earlier in their design process, thus saving time, money, and trouble. In addition, the complexity of today's systems makes the iSDV option a unique choice for testing. Although automation software for single-core SoC systems is difficult enough to create, multicore systems make that creation extremely difficult.
To fully verify our performance SoC bus fabric subsystems, we have to generate all kinds of complex traffic scenarios. Using Questa's intelligent testbench automation we are able to achieve all of our performance and functional verification goals while shaving time off our schedule. With Questa iSDV we can run embedded C test programs with RTL-level testbenches, allowing us to fully verify our system under stressful, but realistic operational conditions, giving us the highest degree of confidence, Galen Blake, Altera's senior verification architect, commented.
The Questa Platform is already an extremely powerful tool for engineering design teams. Likewise, any company that can benefit from software automation is going to find their new iSDV feature is a bonus. In some designs, writing C test programs was once not practical. It was almost an impossible option. Mentor Graphics has put the once impossible task into the hands of companies by creating systems that can incorporate multicore SoC designs. This ability allows systems to become more complex as better, faster, and more sophisticated systems are created.