Linear Technology Corp.'s family of low
power 14-bit and 12-bit, 25Msps to 125Msps analog-to-digital converters (ADCs)
dissipate less than 1mW per mega sample per sec from a 1.8V supply. The LTC2145
family includes two-channel simultaneous sampling, parallel output ADCs, offering
a choice of full-rate CMOS, or double data rate (DDR) CMOS or DDR LVDS digital
outputs with programmable digital output timing, programmable LVDS output
current and optional LVDS output termination.
At 25Msps the 14-bit and 12-bit versions of the LTC2140 consume 24mW per
channel, while the 125Msps LTC2145 consumes 95mW per channel. While claiming
the lowest power dissipation, AC performance has not been compromised. At
14-bits, these devices achieve over 73.2dB SNR performance with 90dB of SFDR at
baseband. At 12-bits, the SNR performance is better than 70.6dB. This A dc
family offers a pin-compatible upgrade path to the low power LTC2185 16-bit A
dc family to provide a 3dB performance upgrade while maintaining portability in
such applications as handheld test and instrumentation, radar/LIDAR, medical
imaging, PET/SPECT scanners, military radios, smart antenna systems and a range
of low-power communication systems.
grade options include 25Msps (24mW/ch), 40Msps (33mW/ch), 65Msps (46mW/ch),
80Msps (55mW/ch), 105Msps (75mW/ch) and 125Msps (95mW/ch). Additional power
savings can be achieved by placing the devices in standby (16mW) or shutdown
(1mW). Analog full power bandwidth of 750MHz and ultralow
jitter of 0.08psRMS allows undersampling of IF frequencies with
excellent noise performance. These devices incorporate Linear Technology's
digital output randomizer and alternate bit polarity (ABP) mode feature for
reduced digital feedback.
Available in 9 x 9mm
QFN packages, designers can benefit from the flexible choice of interfaces that
minimize pin count and ease routing to FPGAs. These A dcs will be available in
production quantities beginning in May through June 2011.
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