Magma Design Automation's hierarchical RTL-to-GDSII reference flow is
for the Common Platform alliance's 32/28-nanometer (nm) low-power process
technology. This reference flow leverages the Talus IC implementation system's
power optimization and management capabilities, the latest ARM Artisan 32/28-nm
LP process libraries and the Common Platform alliance's advanced 32/28-nm
process technology to enable designers to reduce power, turnaround time and
cost per die.
The hierarchical reference design was implemented using Magma's Talus
RTL-to-GDSII flow and the latest ARM Artisan 32/28-nm LP libraries for the
Common Platform 32/28LP process libraries; standard cells, memory compilers and
general-purpose IOs. This design implementation demonstrates that the flow
provides key low-power design capabilities, including an automated multiple
voltage-domain design methodology, validates tool and library interoperability
and facilitates rapid user adoption through the inclusion of a sample design
which can be accessed from Magma or the Common Platform alliance.
Talus Design and Talus Vortex provide an IC implementation solution that
performs timing optimization concurrently during routing - rather than
sequentially before and after place and route - for faster overall design
closure with better performance and predictability. Hydra is a hierarchical
design planning solution for large systems on a chip (SoCs) and features
out-of-the-box reference flows for enhanced ease of use and faster delivery of
better floorplans. Talus Power Pro supports power optimization techniques
required in low-power designs, including multiple voltage domains, which enable
the optimal tradeoff between performance, area and power and clock gating for
dynamic power reduction. Talus Power Pro supports both the Unified Power Format
(UPF) and Common Power Format (CPF) standards for power intent.
The Magma Reference Flow for Common Platform alliance 32/28-nm Low-Power
Process is available upon request from Samsung Electronics, GLOBALFOUNDRIES and
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