iMAPS Conference Identifies Advanced Microelectronics Needs and Solutions
Perhaps the hottest topic at the 2007 iMAPS International Conference and Exhibition on Device Packaging, held March 19-22 in Scottsdale, AZ, was 3D packaging. According to Eric Mounier, a project manager at market research firm Yole Développement, popular 3D packaging technologies include package stacking, die stacking and wafer stacking to achieve minimum area/volume in electronic systems. To implement these packaging techniques, Mounier says enabling technologies include:
• Through silicon vias — electrically isolated interconnections through the silicon,
• Wafer thinning,
• Precision alignment tools and
• Wafer-to-wafer bonding by a variety of techniques.
While all of these topics were discussed, examples of wafer bonding and inspection equipment were available to ensure the performance and reliability of advanced packaging systems typify the tools discussed on the exhibit floor.
Automated Wafer Bonding
The EV Group's EVG540 Fully Automated Wafer Bonding System handles up to four bond chucks. With active bottom side cooling (and optional topside cooling), the unit easily converts to handle wafers or substrates from 100 to 300 mm. For sealing, the unit has a top side heater that can achieve 55C max in 1C steps. Contact pressure for the standard unit is up to 3. 5 kN (790 lb) with options for either 7, 10 or 40 kN. The standard vacuum is 1E-3 mbar with options for 1E-5 mbar and the ability to handle up to four different purge gases. The supported bonding process includes anodic bonding; thermo compression bonding, such as glass frit, metal or eutectic, fusion and silicon direct bonding.
Pattern Writer System
Abeam Technology's XeDraw 2 upgrades a Scanning Electron Microscope (SEM) or focused ion beam (FIB) system to a nanolithography tool. The system's intelligent writing algorithms account for the limited deflection bandwidth of current FIBs or SEMs. With settling time calculations matched to the writing speed and data transmission via USB, the system achieves pixel rates up to 10 MHz. By implementing third order polynomial scan logic, the system generates and writes curved structures such as circles, rings or ellipsoids by concentric single pixel rings (with spline interpolation). The maximum writing speed and approximation quality are achieved with minimum data overhead and transmission time.
Automated PC Board Inspection
The top down three megapixel camera and telecentric lens in YESTech's YTV M1 A01 automatically inspect PC boards for proper solder joints and correct part assembly. Using a standard package library to simplify training, operators typically require less than 30 minutes to develop an inspection program that includes solder joint quality. The image processing technology includes color, normalized correlation and rule-based algorithms that provide thorough inspection coverage with an extremely low false failure rate. The units can be used for paste, pre/post-reflow or final assembly inspection. Inspection capabilities include position error, missing, wrong part and polarity for passive SMT components as small as 01005 size (0.40 x 020 x 013 mm). Solder inspection includes open, insufficient, short and solder balls.