The first in the IES550x family, the IES5501 Bus Buffer Integrated Circuit is made to simplify the design process, using analogue IC design principles for a digital bus. It is used in two-wire bus systems in telecommunications systems, CompactPCI, VME bus systems, RAID products, power management systems, backplane management systems, bus switch/multiplexing buffering and for bus voltage level translation. The buffer doesn't use rise time accelerators, using monolithic bipolar integrated circuit techniques. With low input to output offset voltages, it can be "daisy chained" and/or star configured. The buffer's bus voltages can be level shifted in a range of 1.8 to 15V. The enable pin supports input to output connection control. It comes in 8-pin SO, 8-pin MSOP and 8-pin DIP packages, the latter for sampling only.
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