With the cost of a leading-edge wafer manufacturing facility, or fab, estimated at as much as $5 billion in 2007, many semiconductor suppliers have formed strategic alliances. In late 2006, the collaboration of IBM, Chartered Semiconductor Mfg., Infineon Technologies and Samsung Electronics Co. Ltd. announced first silicon-functional circuits for 45 nm low-power process technology. Kevin Meyer, vice president of worldwide marketing and platform alliances, Chartered Semiconductor, shared his insight for the evolving world of semiconductor manufacturing.
How is today's semiconductor design environment different than it has been in the past?
The business model through the early 90s was an IDM (independent device manufacturer) vertically integrated model, where companies like Motorola would have an application, like a cell phone or a pager, and would carry that design all the way though to the process definition into the manufacturing. That was a highly tuned, vertically integrated technology solution. During the 1990s, we really saw this pendulum swing towards disaggregation and the ability to use off-the-shelf solutions from EDA vendors like Cadence and Synopsys, IP solutions from companies like ARM and libraries from Artisan. People were able to reaggregate the value chain, this vertical chain and develop best-in-class solutions.
What changes have impacted semiconductor manufacturing?
What has happened is that as we continue to move down the technology spectrum, we are coming up against some real physical limits. Historically, we have gone from 5 micron down to 130 nm and it has mainly been a lithography challenge. How do I move the lines closer to each other? As a result of doing that, I get a performance boost because I am sending the electrons shorter distances. I am getting a power boost because I am not dissipating as much energy by moving things closer together. But at 130 we saw the first speed bump in the technology. The capacitance of the aluminum wasn't capable of scaling. Now, we are seeing the gate oxides are getting down to a couple of molecules thick and we are getting tunneling effects through and power loss. So, we are not seeing performance scale as we continue to scale lithography. And, we are having to move to new barrier materials, high K dielectrics, in order to overcome real physical limits for the first time since CMOS was introduced.
How does the collaboration address these challenges?
IBM is one of the leaders in innovation in terms of patents and new technology materials sciences approaches. You've got companies such as Samsung that are solving it from a memory approach. You've got guys like Infineon and Freescale that are having to implement the designs in these new processes. And then, you have Chartered, as a pure play manufacturing component, to make the access available to everybody in the industry. These things are all coming together now to offset the economics and to address the innovation that is required to continue to move the technology down the spectrum.
Is there a 'toughest challenge'?
No. It is an aggregated challenge. In the lithograph, immersion is being used now at 45 nm and below to address the challenges where the historical lithography (approaches) were not going to cut it. How do you get some or the performance back as you scale this and you are up against the physical limits of the gate oxide? There's strain engineering. There's the high K dielectrics. Hafnium is another approach. On the design side, people are going to multi-threshold voltages and voltage islands to address the power consumption at the chip level. All of this is going to have to come together to be able to continue to scale and be able to get the performance that people have traditionally gotten following Moore's Law.
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