Successfully Fabricating 65 nm Designs

For Chartered Semiconductor Manufacturing, one of the world's top dedicated semiconductor foundries, a smooth customer transition to 65 nm and even 90 nm required a design-for-manufacturing (DFM) effort up front. Working with industry leaders, International Business Machines Corporation and Samsung Electronics Co. and a number of tool suppliers, the goal was faster design decisions by understanding the tradeoffs early in the design process.

"We see the technology moving very quickly," says Walter Ng, senior director, platform alliances at Chartered. "A number of customers, if they haven't already moved to 90 nm, are looking at going from 130 nm to 65 nm." Ng has been involved in the company's design-for-manufacturing strategy. To make this technology leap, Ng identifies two critical issues.

"Power is a huge issue," says Ng. "In our technology roadmap, we actually switched the order. At 90 nm we had the nominal process or generic process available for customers before the low power process." Many of the companies working in the 65 nm area are large, fabless companies who have designs that integrate several functions and have extensive reuse. These large, integrated designs have significant power requirements. Chartered's 65 nm process supports multiple voltage thresholds that help designers reduce power consumption. The process capability gets translated to the design side in the form of libraries that support multi-threshold design methodology. Those parts of the design that require very high performance have library cells and use the associated wafer fab process. Those portions of the design that do not require high performance use a process with voltage thresholds that do not require as much power. On the design side, engineers implement many

different schemes to reduce power consumption. "From a process standpoint, we are trying to support them with process technology that has multiple thresholds and also supports multiple voltages," says Ng.

The other critical issue with any smaller geometry process is the tolerances. "We are dealing with variations, and at 65 nm small variations can be very significant," notes Ng. To manage this variation and allow its customers to manage it, Chartered brought awareness of the manufacturing tolerances back into the design phase. This allows designers to make decisions for robust manufacturing and high yields in a timely manner.

The Common Platform Technology developed by IBM, Samsung and Chartered allows users to make relevant tradeoffs early in the design cycle. In addition to manufacturability, the methodology addresses timing, area, power and signal integrity.

"With regard to the differences in manufacturing 65 or manufacturing 90, there really isn't that much difference," says Ng. "There aren't significant new material changes. There aren't significant equipment changes. So the transition from 90 to 65 should be relatively smooth."

For more information on Chartered Semiconductor Manufacturing technology, go to http://rbi.ims.ca/4925-501.