Materials and equipment play a key role to make “smaller, faster and higher performance” a continuing reality in the semiconductor industry. Perhaps one of the most pervasive subsystems in wafer processing is motion control. Air handling and filtering to sawing and dicing and all the steps in between (layering, patterning, doping, vapor deposition, polishing and heat treatment) rely on linear and/or rotational motion. Two key processes using motion control are photolithography and Chemical Mechanical Planarization (or Polishing) (CMP).
“In terms of the evolution of processes for making smaller and smaller devices, the two critical activities that take place are shrinking of device geometries of the printed lines and features on the wafer and then stacking of layers toward taller and taller structures with more and more intricate interconnections among them,” says Rob Rhoades, chief technology officer, Entrepix. The two processes that tend to be the most critical for these activities are CMP and photolithography. Photolithography is the process used to pattern the structures on the wafer and CMP is used to planarize layers at intermediate points in the construction of the device so there is a flat and smooth surface for depositing the next layer.
How CMP Stacks Up
For leading-edge wafer processes, the number of interconnect layers continues to increase. “I think the most advance technologies that are being utilized are up to 12 or 13 layers of interconnects,” says Bob Tucker, vice president and general manager, Entrepix.
Initially used in the interconnects almost two decades ago, CMP kept features in focus during the photolithography process. CMP planarized oxide layers as the interlevel dielectric before patterning the next level of metal. The technique expanded to include several other process steps such as stacked vias and shallow trench isolation.
“There are now up to 10 or 11 or even more materials that are planarized with CMP in various implementations of modern process flows,” says Rhoades. Each one of those materials requires a new development effort. Typically, it is a completely different process with a different slurry, a different set of chemistries involved and a whole list of process interactions that have to be characterized and controlled in order to bring the new process into reliable mainstream manufacturing.
“A lot of people think the most difficult integration is the ultra-low K (ULK),” says Rhodes. ULK dielectrics generally target an effective dielectric constant of 2.5 or less and many of the techniques involve nanoporous films. The film itself has voids, spaces in the material that are very microscopic on a nanoscale. As a result, it does not have a high mechanical integrity. Polishing this material or the film deposited above it can easily cause cracking, delamination shear forces that can cause different failures in the stack.
The polisher itself has a vertical shaft that applies the load in the area of 100 to a few 100 lb of force while the wafer is spinning in a carrier at the end of the shaft. Under that assemble is a separate platen, or flat plate with a polishing pad attached. A thin layer of slurry flows on the surface of the pad lubricating the interface of the wafer and the polishing pad. The chemistry and tiny abrasive particles in the slurry provide the consumables and form the secret sauce for CMP.
The surface of the pad provides a controlled texture for the polishing operation. It has to be maintained and kept consistent as it polishes wafer after wafer. The refreshing of the surface is done with a pad conditioner. A new style pad conditioner develop by Entrepix, called SteadySweep, enables less and more accurately applied down force. “SteadySweep implements a completely different mechanism for controlling that pressure,” says Barry Cooley, equipment sales manager, Entrepix. Watch the video here. “The older style pad conditioner that it replaces uses a linear translator motor in the vertical dimension and a feedback loop.
The traditional pad conditioner senses a pressure, moves the pad up if it is too high or adjusts it down if it is too low. However, the feedback loop and the associated time delays cause a problem when everything is spinning and moving. By the time the feedback loop detects an off-target pressure, many seconds have elapsed and the conditioner is in a different position on the pad. The SteadySweep uses more of a hydraulic technique to maintain constant pressure even if the vertical position of the conditioner rides up and down on the rotating pad.
With finer and finer geometries, defectivity is an increasingly critical aspect. “The sizes of features that are being patterned on these wafers are so incredibly small, you can stack 50 or 100 of them side by side and still not make the width of human hair,” says Rhoades. Shedding of particles or lubricants that outgas materials such a zinc or potassium cannot be tolerated. Concern for lower contamination levels is driving new specifications for moving and rotating components that dictate different bearings or materials or shrouds to isolate them from the process area. And the specs differ from OEM to OEM.
Turning to the Motors
Motors used in semiconductor manufacturing frequently require special consideration. “There is like 27 different factors in the electromechanical design of a brushless servo motor that affect its torque characteristics in various ways, including the ripple of the torque, the smoothness of the torque, etc.,” says Bob Brennan, business development manager for the U.S., WITTENSTEIN motion control. WITTENSTEIN makes integrated brushless servo motors with direct drive as well as integrated units with precision gearhead systems.
Brennan recalls one application where a customer had a particular problem with accurately controlling speed, acceleration and deceleration in a wafer process with critical concern regarding wafer handling, as well as minimizing the heat contribution of the motor. “We had to integrate a high pole count motor into a system,” he says, “with a special design in order that heat did not get added to the process.”
In addition to addressing extremely smooth torque regulation, very low cogging (in the milli-Newtons of torque ripple) and very high efficiency multi-pole motors, Brennan says they have qualified a number of systems in a clean room environment. To minimize outgassing that could affect the controlled environment, special materials are used in the motor and special attention is given to the bearings and the types of greases used to lubricate them.
Another specific motor control application occurs at the end of the wafer process during inspection. Frequently, step motors are run at various microstep settings to ensure accurate steps and smooth motion. “Lin Engineering's 3509V step motor is a 0.9-degree NEMA 14 motor that has recently been successfully used in a wafer inspection machine,” says Kenneth Nip, engineering manager, Lin Engineering. In addition to its small size and adequate torque, the 3509V provided extremely accurate, smooth motion.
In terms of accuracy, the 3509V motor maintains ± 1.5 arc min error under 1/64 microstepping while the industry standard error range for a 0.9-degree step motor is ± 4.5 to ± 18 arc minutes. This means each step the motor takes is 0.9 degree divided by 64, or, 0.014 degree. With every step, the maximum error from the 3509V step motor is a mere 0.025 degree.
Lithography: Picture This
Lithography systems such as ASML's XT:1900i, use a photographic process to image nano-scale circuit patterns onto a silicon wafer, similar to the way a camera prints an image on film. Announced earlier this year, the XT:1900i operates at a 1.35 numerical aperture (NA) and a 193 nm wavelength compared to the prior generation XT:1700 with a 1.2 NA. “The 1900 is the highest NA in the industry that is capable with water as the immersion media,” says Skip Miller, director of strategic marketing, ASML.
NA drives imaging capability to obtain smaller and smaller resolution. Higher NAs require water immersion because of the optics of the lens and the wafer. “At NAs below one, you can run the system in a dry mode or a wet mode because you don't need the refractive index of water to image,” says Miller.
The 1.35 NA of the XT:1900 enables around 40 nm capability. “We say we will capture less than or equal to 40 nm half pitch, which for the logic world that means the 32 nm node,” says Miller. However, NA is just one aspect of lithography for smaller structures. Overlay is another critical area.
Overlay refers to the positioning of one mask layer over the other, such as a poly or gate layer to an active layer or contact to gate or metal to contact. With improved overlay capability, a smaller cell area can be achieved, shrinking the overall die size. For example, ASML evaluated an aggressive, typical and relaxed overlay on a cell design. Using an aggressive overlay on a 45 nm technology, the cell area went from 0.27 micron squared to 0.2 micron squared. However, to have sufficient process capability for high yield, designers may not want to operate at the most aggressive level. “Anything you can give them in terms of better overlay or imaging capability will translate into the smaller die area,” says Miller.
Increased productivity is another design goal with each new generation. In a wafer fab, productivity means completed wafers/hour. “It's a function of how fast you can accelerate and move your stages,” says Miller. At a scan speed of 600 mm/sec ASML scanners move a small slit of light across a field size of 26 × 33 mm at a speed of 600 mm/sec for the XT:1900 (550 mm/sec for its predecessor, the XT:1700). Other factors include acceleration, alignment time and exposure dose. With today's stage technology, the XT:1900 will run 130 wafers/hour at 600 mm/sec scan speed. “With each generation there are improvements on these speeds and different delay times and accelerations within the stage area, the mechatronics area,” says Miller. To achieve these kinds of improvement, ASML works with its suppliers to obtain the latest high-performance motion control systems.
ASMLs TWINSCAN approach in its XT:1900i and other scanners uses two linear Maglev type stages under X-, Y- and Z-axis interferometer control. To make the most cost-effective tool, while it is exposing one stage under the lens, the other stage performs alignment and focus leveling, mapping out the whole wafer from an X, Y and Z perspective. “When the other wafer under the lens is done, the mapped out wafer can zoom under the lens and be exposed without having to do any feedforward/feedback. It's already mapped out,” says Miller.
Miller puts the motion in today's lithography system into perspective and says, “You are moving this thing at 600 mm/sec, therefore pumping out 300 mm wafers at 130 wafers an hour and on top of that you are doing this with an accuracy of on the order of 5 nm.”
The Small Picture
Moving forward, ASML sees an even greater link between the IC design and lithographic process.
Initially, IC designs went directly to lithography and from lithography to inspection and lab-based metrology. With the shrink levels below 180 to 130 nm, enhanced interfaces between these groups have been created. The amount of complexity below these levels requires reticle enhancement techniques or design correction to obtain consistent lines and spaces. Bridging the gap requires knowledge of both lithography and design parameters. Visualize a dual versus single lithography sweep.
With the availability of the XT:1900i later this year, ASML has its near-term solution for lithography going down to the 32 nm node. “The future out beyond that is currently in a big state of discussion right now,” says Miller. Potential solutions include double patterning and extreme ultraviolet or EUV.
In double patterning, instead of printing a 32 nm line and a 32 nm space at one time, the pattern is split to print essentially a 64 nm line and patterned two times to get to the end 32 nm feature. EUV (typically less than 180 nm) is a possible next-generation wavelength technology for 13 nm processing. “That's the debate on the future right now,” says Miller.