Where does Texas Instruments stand in the development of 65 nm technology?
To give you a little history, we qualified our 90 nm for production at the end of 2003, and we typically release a new node every two years. This year, we already have samples of our new 65 nm chips in customers' hands, and we expect to be in volume production by the end of this year.
What is your first chip in the 65 nm node?
It's a wireless digital baseband chip used in such applications as cell phones. These chips have an embedded DSP (digital signal processor), microcontroller, ASIC (application-specific integrated circuit), and embedded SRAM (static random access memory). So it's a system-on-chip architecture.
What type of photolithography system are you using?
It's a dry system with a high numerical aperture and a 193 nm ArF light source. I don't know of anyone in the world who is planning immersion lithography for 65 nm production.
Will immersion lithography be needed for new generations of chips?
Yes. We are looking at immersion lithography for our 45 nm node, which we are targeting for volume production in late 2007 or early 2008. This allows time for equipment manufacturers to have new immersion systems ready. One of the issues that the equipment manufacturers have to resolve is that their first immersion machines still have numerical apertures (NAs) below 1.0—typically 0.92 or 0.93. We believe that NAs below 1.0 are not capable of 45 nm printing. So we are anticipating a second wave of machines from the equipment vendors with NAs above this 1.0 minimum in order to achieve the resolution and depth of focus we need for next-generation chips.
Where do the chief challenges lie in perfecting immersion systems?
Certainly, the optics are very important, such as developing projection lenses with high NAs. But overall the lithography equipment suppliers are learning about immersion technology right along with their customers. ASML, Nikon, and Canon are all offering dry lithography systems with NAs around 0.93, and their first step was to add an immersion stage to those platforms.
How important are the motion control systems in these cutting-edge lithography systems?
This year, Texas Instruments begins volume production of its 65-nm chip, which features an embedded DSP (digital signal processor), microcontroller, ASIC (application specific integrated circuit), and embedded SRAM (static random access memory).
They are extremely important. The wafer stage needs to move very fast to meet throughput requirements. Then you also need to change directions with the scanner, and you've got to minimize recoil in such maneuvers. Small nuances in those movements are very critical when you start patterning 65 and 45 nm chips. Lithography systems also must address the challenges created by the industry trend of producing more system-on-chip designs, which tend to be larger chips with more and more functionality. As chip sizes get larger, we need to make sure that there is very good lithography pattern control to maintain tight critical dimensions (CD) across the entire chip. Most scanner manufacturers have done a good job of controlling CD at a wafer level, but they are only now addressing what it takes to control CD within a chip or inside one shot.
How about challenges for semiconductor designs as you move from the 65 nm node to 45 nm?
As we scale down, we need to investigate new low-resistance materials, such as nickel. We also need to develop both circuit design and process techniques to address leakage problems in transistors, which occur as you scale down. This is particularly important for us at TI because our wireless chips are used in handheld devices, such as cell phones, PDAs, and digital cameras, where long battery life is important. At the same time, as you address leakage problems, you don't want to slow the transistor down. This is why we are working with strained silicon technology and other techniques to improve transistor performance and switching speeds.
Dr. Venu Menon, who joined TI in 1995, oversees 130 nm and 65 nm development. Prior to this assignment, he served as program manager for the 180 nm node, where he led the first copper process introduction for 180 nm. He holds a Ph.D. in chemical engineering from the Illinois Institute of Technology.