In industrial applications, a digital-to-analog (D-to-A) interface may be rather straightforward but the analog-to-digital (A-to-D) converter (ADC) can be a challenge. The capacitive input stage of both delta-sigma and successive approximation register (SAR) interfaces used for the ADC requires signal capture within a limited time frame. An improper signal chain can cause ringing and oscillation and result in inaccurate readings. However, this is just one of many factors to consider when selecting an ADC.
High-performance ADCs convert the output of an analog sensor to a digital format for a microcontroller or digital signal processor. The selection of the ADC must be part of a systems approach. “When somebody starts a design, you start with the sensor, you see what kind of output impedance it has and you choose an amplifier and resistors around the amplifier and you choose that configuration based on your sensor,” says Chuck Sins, applications engineer, National Semiconductor. “Based on the accuracy of your sensor and what you are ultimately trying to achieve, then I choose the resolution of the ADC.”
“Basically you have the sensor, amplifier and ADC that have to work in concert to provide sufficient performance for the application,” adds Dave Potson, senior design engineer, data conversion division, National Semiconductor. “Obviously, dc precision requirements have to be there, the noise requirements have to be met and the bandwidth requirements have to be met depending upon the speed of the signal you are processing.” The amplifier contributes a large portion of the dc requirements, especially if the sensor signals are small.
For the ADC, static performance includes integral non-linearity (INL), the maximum departure of any code from the ideal transfer curve, which is a measure of the straightness of the transfer function curve and differential non-linearity (DNL), the measure of maximum deviation from the ideal step size of 1 least significant bit (LSB). However, there are dozens of specifications that thoroughly define the performance of an ADC.
One of the key system design factors is avoiding ringing and oscillation. “Amplifiers have stability issues driving capacitive loads and the input to the ADC is a capacitive load,” says Alain Guery, marketing and applications manager for precision converters, Analog Devices Inc.
To convert signals up to megahertz levels, a successive approximation register ADC uses a capacitive array at its sample/hold input. “When you go into track mode, you get this big disturbance at the input,” says Sins. “As long as that disturbance settles out by the time we enter hold mode, and hold mode is when that switch now opens and the voltage on the capacitor array is now evaluated by ADC, as long as it settles out, there is no loss in accuracy.”
Designers have reduced the size of the capacitor array to values in the 20 pF range, so the capacitor filter required to smooth out the disturbance is much smaller. “The rule of thumb that we throw out there is a 10 to 1 ratio,” says Sins. “If the input capacitor is a 20 pF value, as long as you have an external capacitor that is in that 10x kind of range, there is not much of a disturbance at the output. You’ll see a ¹/10 deflection at the input so there is not as much voltage to recover to get an accurate reading.” In general, a 470 pF value works for kilohertz level and dc signals with a relatively small (20O) resistor in series.
Power consumption is an area that has improved dramatically in recent years with portable sensing applications in industrial and medical instruments providing a driving force. “Our power is now down to 10 mW for 12-bit 1-MHz converters and for 16-bit converters, 1-MHz converters right down to 12 to 13 mW level. Five years ago we were talking about 150 to 200 mW for those same types of converters,” says Don Travers, worldwide marketing manager for precision analog, Texas Instruments. “You are talking about a factor of 10 less in power.”
An example of TI’s low power ADC is the recently introduced microPower ADS8317. Designed for battery-powered applications including industrial data acquisition and portable medical instrumentation, the 16-bit analog-to-digital converters consume 10 mW at 5V when operating at the full data rate of 250 kilo-Samples-Per-Sec (kSPS). At 200 kSPS, power dissipation is less than 4 mW at 2.7V.
In its PowerWise ADCs, National Semiconductor has a power down feature in addition to extremely low power consumption over a range of sample rates. For example, a single channel 1MSPS PowerWise ADC used in a 10 kSPS application has a typical power consumption of 0.02 mW at 3V.
Other System Factors
Another factor that impacts both the ADC and the amplifier is noise considerations. “You can take an amplifier and integrate its noise over the bandwidth of the ADC and you have to try to keep it less than that,” says Rich Capistran, applications engineer, precision converters, Analog Devices. With a typical signal to noise ratio (SNR) of 47.3 in Analog Devices’ AD7980, the SNR degradation can be calculated by:
f–3dB is the input bandwidth in MHz of the converter (in this case, the AD7980’s 10 MHz) or the cutoff frequency of the input filter, if one is used.
N is the noise gain of the amplifier.
eN is the equivalent input noise voltage of the op amp, in nV/Hz.
Evaluation boards have become the universal offering in the IC industry to reduce time to market and ADCs are no exception. “It’s all about getting to market as quickly as possible,” says National Semiconductor’s Sins. Certainly, the trade-offs are simplified if the user can connect the board between the sensor and the digital computing portion and it simply works.