The Path to Future Production

What challenges do semiconductor manufacturers face below 100 nm?

With every tighter resolution process node, there are always some difficulties. However, it's best to characterize the difficulties by degree. The transition from 90 to 65 nm was not as difficult as from 130 to 90. That is because process engineers learned a lot of lessons with regard to interlayer and intralayer dielectrics — that's the insulation that separates the copper "wires" on a chip one from the next. The dielectric constant needs to be low in order to prevent cross talk and signal loss when signals are transmitted at high speed through the copper runs. Copper metal runs are formed in a process known as a damascene process. That is where an insulator layer is deposited, then is etched out to form trenches, filled with copper, and then "sanded" flat. That's different than what we did with aluminum. And, we learned most of the lessons in developing a damascene process at 130 nm, so that wasn't a tough lesson at 90.

Is there another area below 100 nm that causes special concern?

You need to do some special things to make lithography work, when the wavelength of light is actually bigger than the line you are trying to define. Resolution enhancement techniques or RET involve things like tricks with masks. Picture a corner of a line that you are trying to define in photo resist and then eventually on the chip. As you get smaller and smaller in dimension, that corner doesn't look like a corner anymore. It looks like a rounded edge — like a quarter piece of molding. What we learned to do is instead of having the mask look just like a square comer, we put a serif, a little square bulge in the edge of the corner so more light gets through right at that corner. When you print that line in photo resist, it looks like a square, or at least more like a square. Then when you transfer that pattern to the semiconductor device, it looks like a square — not so rounded anymore. It's called OPC, optical proximity correction.

Any additional problems at the next transition from 65 to 45 nm?

When we go from 65 to 45 nm, we no longer can use light that is at 193 nm wavelength. We need to do something else to define those 45 nm features. The industry has gone towards what is known as Immersion Lithography, or IL. In Immersion Lithography instead of using air between the lens of the stepper and the photoresist on the wafer, a layer of liquid is deployed. That is, we immerse the wafer in liquid. Today it's water. Tomorrow it might be some other liquid. This permits better coupling of the light information that's transmitted through the mask to the photo resist, so you get better resolution. It looks like, for 45 nm, the industry will need to use immersion lithography.

Can you provide an example of an immersion lithography that has addressed the sub-100 nm challenges?

Most definitely. ASML has had to develop a way to dispense liquid, water in this case, and extract it while they are exposing and not create bubbles or particulate defects at the same time. ASML is fortunate to have a dual-stage system, which means you can do some alignment in one stage and move the wafer to another stage and dispense the water, extract the water, and in-between do the exposure. So a dual-stage system provides an advantage for ASML and they are a leader in Immersion Lithography. But it is worthy to note that Nikon has a very viable IL tool, as well.

Are there control systems, networks or other technologies the semiconductor companies enable that are used to help them do a better job in manufacturing their own product?

There is whole realm of process control called APC (Advanced Process Control). What that effectively means is you control certain sections of your process, automatically. And this means not just controlling, but controlling to a more favorable degree, say producing MPU chips with average high speeds. So if you have superior APC, you are able to produce higher yields and produce products that are closer to the ideal specification. The most advanced fabs in the world are still implementing APC.

With the challenges of 65 and 45, will they be implementing APC further?

Even more so. Right now, it appears that the best processors have widely implemented APC and the second tier are trying to do so. Who knows, maybe in five or 10 years this will be common knowledge.