Within the next three to five years, design engineers could have at their disposal new CMOS (Complementary Metal-Oxide Semiconductor) computer chips that are 40 to 65% faster than the chips currently used in computers. Those lightening-fast chips could power web servers, personal digital assistants (PDAs) and other portable devices, or engineering workstations that could enable dramatically faster simulations and analyses of designs.
IBM scientists have developed the chips using so-called strained-silicon-directly-on-insulator (SSDOI) technology. Strained silicon is silicon whose crystal arrangement has been enlarged by about 1% by stretching the top silicon layer with an underlying layer of silicon germanium. The result: Electrons will flow through faster. The insulator is located in between the transistor and the substrate so that there is no leakage.
In IBM's process, scientists remove the germanium layer after enlarging the crystal arrangement and before actually fabricating the chip. That step, says Mei Kei Ieong, IBM's senior manager of exploratory devices, avoids the heat-dissipation problems normally associated with germanium. "The process for making chips is different with germanium, and we don't have enough experience to optimize the process," he says.
CMOS technology is the backbone of electronics devices because of its high-performance and low-power capabilities. But the technology is approaching its limits in terms of scalability, so the computer and semiconductor industries have been working hard to find new technologies for making electric charges move faster through chip-device channels to increase circuit speeds and lower power consumption. In related activities, HP and Dell have designed new workstations based on Intel's Itanium 2 chip.
IBM will present the details of this latest technology jump at the International Electron Devices Meeting, December 7-10 in Washington, DC.