Manufacturing Challenges

For semiconductor technology, forecasting 2013 is the near term. The long term projections in the 2005 update to the International Technology Roadmap for Semiconductors (ITRS) cover 2013 to 2020. In the next seven years, the industry has identified specific parameters that will improve and the many challenges that will have to be addressed.

At the 2006 Semico Summit in Scottsdale, AZ, industry experts addressed some of these issues. Jim Feldhan, President, Semico Research Corp. believes that disruptive technology solutions for low leakage ICs and new lithography will drive market growth.

Special design tricks like resolution enhancement techniques or RET are already used to make lithography work when the wavelength of light is larger than the line to be defined. One example to avoid a rounded edge adds a serif, a little square bulge in the edge of the corner, to allow more light at the corner. This optical proximity correction or OPC produces lines in photo resist and patterns on semiconductor that are closer to the desired square shape.

In his keynote address, Sir Robin Saxby, Chairman of ARM noted that compared to the 1986 ARM1 design at 3.0 µ with 25K transistors that were 50 mm², a 2006 ARM7TDMI design at 65 nm has 100K transistors that are less than 0.1 mm². The scaling that has occurred over that time also includes scaling for power, which has dropped from 20 to 0.025 mW/MHz.

According to Dave Cavanaugh, director of manufacturing technology for Semico Research (See the Q&A, The Path to Future Production, page 24), there are two popular techniques to achieve increased performance while keeping power dissipation low. One uses silicon on insulator (SOI) wafers and the other is known as strained silicon techniques. With strained silicon, squeezing the gate or stretching, pulling apart the gate of the transistor increases hole or electron mobility. This technique increases performance 30 percent or more without having to use SOI. Since SOI is a costly approach, postponing its use is considered an important strategy by some manufacturers.

	A strained silicon channel in Silicon Germanium (SiGe). Strained silicon provides increased performance with lower power consumption. Courtesy IBM.

At some point Cavanaugh insists, "The physics of having to build devices on SOI wafers becomes compelling." This could be a 45 nm, but certainly at 32 nm to reduce the off state leakage. However, at 65 nm, there are two camps. One that includes IBM, AMD, Chartered Semiconductor, Sony, and Toshiba that currently uses SOI wafers. The other camp, with leaders such as Intel and TI, has chosen to use strained silicon and other techniques.

The different choices to meet the future performance requirements including reduced leakage, low power operation, and increased power density should make for interesting competition.

For more information on strained silicon, check out http://rbi.ims.ca/4925-500.