Crolles, France – As semiconductors move into ever finer geometries, the challenges of testing and packaging them are growing exponentially. Three major semiconductor companies are expanding their alliance to solve some of the vexing issues that come with the move to 90 and 65 nanometer line widths.
The Crolles2 Alliance, comprised of Freescale Semiconductor, Philips and STMicroelectronics, is establishing a new research laboratory in Grenoble, France, to examine techniques for all aspects of post-fabrication wafer processing including probing, grinding, sawing, die attach, wire-bonding, flip chip and package molding techniques.
About 20 scientists will be hired to explore processing of large 300 mm wafers that have 90 and 65 nm line widths while looking forward to 45 nm geometries. The new scientists in Grenoble will complement a staff of more than 1,000 employees working on front-end fabrication processes in nearby Crolles.
They will focus on mechanical techniques for probing and testing die. “The inner layer dielectrics used today are too brittle at those line widths, so mechanical damage can occur when they’re probed,” says Andreas Wilde, Freescale technology director for the Crolles2 Alliance.
Attaching wire bonds to these tiny pads also becomes much more difficult as line width shrink. Expanding research in assembly and test will help the companies stay on track with the International Technology Roadmap for Semiconductors, which is revised annually by an international staff from major companies and universities.
The three Crolles2 Alliance companies formed their alliance early in 2002 and have already benefited from its research, which focuses on common technologies that don’t infringe on areas where the companies compete or want to maintain proprietary technologies. “The alliance has proven extremely efficient at allowing us to complement each other’s competitive technologies,” Wilde says. The new testing techniques will complement boundary scan testing, he adds. The current consortium plan goes through 2007, when researchers will be focusing on 35 nm technologies.
Fragile Parts. Processing wafers with 90 nm or smaller lines is changing the way chips must be tested and packaged.