Specifications for analog-to-digital converters (ADCs) often include a fast Fourier transform (FFT) plot, such as the one shown in the figure, for a 12-bit ADC with a single-frequency input signal. In this case, a 12-bit Maxim MAX1420 ADC with a 60.049MHz sampling frequency (fs) sampled a 2.126MHz input tone with an amplitude of -0.5dB (full scale). The FFT plot shows harmonics at 4.252MHz and 6.377MHz due to device nonlinearities, and the FFT indicates a noise floor at about -104dB.

An ideal N-bit ADC has a theoretical signal-to-noise ratio (SNR) of (6.02*N)+1.76dB, or roughly 74dB for a 12-bit converter when driven by a full-scale sine wave. Here the term "noise" refers to ADC quantization noise. But when plotting the FFT results for the test described above, this theoretical value appears worse than the measured noise floor. This difference, called FFT processing gain, arises from the nature of the FFT, and you must keep it in mind when you examine such plots to evaluate ADC performance. You can estimate the FFT processing gain using the formula:

FFT gain = 10*log(M/2)

M equals the number of points processed in the FFT. In the earlier example for M=4096 points, the FFT processing gain amounts to 33dB. But what causes this gain?

By its nature, an FFT frequency bin has an amplitude response of sin(x)/x, so the value in each bin arises mainly from its main amplitude lobe. According to the signal processing practitioner Richard G. Lyons, we may think of the value of the mth FFT bin as the output from a narrow bandpass filter with a center frequency at mfs/M. Increasing the number of ADC samples used in an FFT decreases bin bandwidth and increases bin amplitude. A larger number of samples also improves frequency resolution and decreases the amount of noise in the bin's passband. Doubling the number of samples, for example, decreases noise power in a bin by 3dB. Thus, when you process a signal with an FFT, you can dig out signals from background spectral noise.

Lyons writes in his book Understanding Digital Signal Processing: "The discrete Fourier transform's [DFT] output SNR increases as M gets larger because a DFT bin's output noise standard deviation (rms) value is proportional to √M, and the DFT's output magnitude for the bin containing the signal tone is proportional to M."

When you analyze information for the performance of an ADC and refer to an FFT plot, remember that the FFT noise floor will not represent the SNR for the ADC. For that information, you use the calculations shown earlier and account for the FFT processing gain.

For More Information:

Richard Lyons, Understanding Digital Signal Processing. Hoboken, N.J.: Prentice Hall, 2010. pp. 102-105.

I remember how FFT were both a bane and a boon in engineering school. Fast Fourier Transforms are at the heart of communications theory, and are actually very interesting. At the same time, the initial learning curve, while not step, is not trivial either. On the implementation side, an flexibility you can gain regarding setting the parameters you want for digital signal processing apps is a significant design advantage, so this is a valuable article by Jon.

Once, when I was using FFTs a lot, I took an advanced math course at a university (I was going back to school to complete a degree). Transforms figured a lot in this class (LaPlace, Fourier). When we got to Fourier Transforms (DFT) I was waiting for some insight from the professor on the FFT. I was implementing these for some complex signal processing research projects. Finally, I went up to the professor and asked about the FFT. He looked at me blankly and I felt really dumb. So, I went home and looked at my books of the FFT (I had several, and fortunately the company was paying for them). So, next class I explained what I was interested in. His response was that he was a theoretical mathematician. He did not care how long it took someone like me to comptue it. Live and learn.

Jon: Lyons appears to be saying that the signal-to-noise increases as the FFT processes more points. So if I'm a mechanical engineer employing an ADC in my product, what lesson I can learn from this?

When you look at the FFT plot in an ADC data sheet, it's easy to mistakenly interpret the results as showing a noise floor lower than expected, and thus a expect the ADC to deliver a larger signal-to-noise ratio. The more points you take, the better the plot looks because of the way the FFT spreads energy among the various frequency bins. The plots of FFT results don't tell the whole story, so use them with care and pay attention to the numeric specs the ADC manufacturer provides. Or better yet, get some IC samples, or ask for a "loaner" ADC module, and run some tests in your own measurement environment. I also wanted to show there's a mathematical reason why the FFT plots look the way they do.--Jon

While it is true that SNR improvements can be enjoyed at the expense of reduced bandwidth, "there ain't no free lunch". By the very definition, FFT implies a sampled system. So if we are using a sampled data set as opposed to a continuous time analysis using DFT, where is the discussion on the sampler?

Life would be pretty easy if the signal world existed of singular tones but in the real world the signals we need to resolve occupy more than 1 bin of the FFT. (can I interest you in a jar of OFDM?)

While it is true that the processing gain in dB is 10*log(BW1/BW2) if BW2 is smaller than BW1, there are 2 additional parameters that are critical to achieving the ideal improvement in the aforementioned equation.

Settling time and aperture jitter cannot be ignored.

For example if it is desired to resolve a 4.096 V full scale signal to 12 bits accuracy at 10 MHz sample rate, the analog path has to settle to within 1 mV of the final value in 100 nS. Can you say "40 volts / uS slew rate"? If the amplifiers can't do that say goodbye to best case 74 dB SNR no matter what the FFT processing gain is.

If the clock is noisy, well you know the answer by now. If you want to get the SNR out of that 12 bit 10 Ms/s ADC better be sure to keep the clock jitter to 2 pS.

Thanks for your comments, Don. You are correct about accounting for the jitter and settling time in ADC measurements. It's sometimes difficult to get everything in a 400-word column, so the January column discusses where the "noise" in a signal-to-noise ratio (SNR) comes from. I included information about jitter and can cover this aspect to measurements in other column, too. The January column lists several good references. Again, thanks. --Jon

Suppose you wanted to create a FIR filter with your own requirements. How would you find the necessary coefficients, and how many of them would you need?

Switched-capacitor filters have a few disadvantages. They exhibit greater sensitivity to noise than their op-amp-based filter siblings, and they have low-amplitude clock-signal artifacts -- clock feedthrough -- on their outputs.

The Machinist Calc Pro computes speeds and feed rates for milling, turning, and drilling: cutting speed, spindle speed, feed rate (inches/minute), cutting feed, etc.

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