Are you designing for testability? If you think that even simple designs don’t need test points, you are wrong.
Circuit scale continues to follow Moore’s Law, even to this day. When 0403 becomes 0201 and then becomes 010005, the scale is almost beyond direct human manipulation. At these sizes, using component solder connections as a test point is possible but unserviceable. “But the design is just a simple RC circuit, no need for a test point.” No, seriously, this is the wrong mindset. Designs change, expand, conflict, and errors abound in early versions. Catching errors early will save 10 to 1,000 times the money to solve. Due diligence ahead of time is key.
There are few inevitabilities in life -- death, bills, taxes -- and problematic designs should be added to that list. That said, Design for Testability (DFT) is essential in these days of system on a chip (SoC) and components that are smaller than the point of a needle.
Altium’s 3D Single Layer Mode, showing a clear view of a particular layer.
The requirements stage of any design is the most critical. An error in this stage will snowball complications and cost more to fix later. Let us assume this stage is done thoroughly and correctly. The next important stage of the Product Life Cycle (PLC) is the design phase. This is where the true inception of the product/design, the true initial error, is created. It’s unavoidable. After which, that error could snowball throughout manufacturing/assembly and become extremely costly by the test/integrations phase.
To put the concept more scientifically, NASA published a report called "Error Cost Escalation through the Project Life Cycle." An error at the requirements stage was given an arbitrary “1 unit.” The costs to fix the error during the design phase ticks up to “3 to 8 units.” If that same error was addressed at the manufacturing stage, the cost then moved up to “7 to 16 units.”
Addressing that error during the test and integration phase brings the cost up to “21 to 78 units." Fixing an error after a product has been released into the market would cost “29 units” to a whopping “1,500 units.”
At $240 a day ($30 per hour), an engineer could fix a problem for 3 units, or $720. Let it go to the public, and it could reach 1,500 units, or $360,000 to smooth out that wrinkle. The design phase is the gateway point, bridging ideas with the real world. It is extremely critical to stop the dominoes of error from falling any further past this point.
There are many points in the product life cycle that can introduce errors, but not every point is a hardware engineer’s concern. The engineering ringmaster of the hardware design phase has the most critical job. Software can easily change on a whim, hardware cannot. Unfortunately, poorly structured software can affect the system so harshly that the hardware design will be questioned. Even if software is not involved, it would behoove the hardware ringmaster to plan ahead, make the worst case assumptions, and plan to test every aspect of the hardware, no matter how simple the design.
Luckily, most PCB layout programs can help supply test points automatically. It’s the simplest form of DFT a hardware designer can apply to their designs.
Cadence's Encounter family offers a complete test flow from concept to the silicon for ICs and SoCs.
Altium Designer, the low-priced, full-featured circuit design suite, has what they call the Testpoint System. Buried deep in the software package features tree, the Testpoint System allows the user to automate the process in applying test contacts. Of course, manually setting points is always an option. Altium 3 suggests considering where, and how many, test points are assigned to a PCB to save cost. As shown above by NASA engineers, the earlier an error is caught, the cheaper it is. So, in this case, don’t listen to Altium. Spare no expense in the design phase.
Altium has test point style and usage guides for both the fabrication and assembly stages of the design cycle. Altium’s “Design Rules” lets the user set some “well-honed set of design rules.” This translates overt to the PCB editor to constrain the schematic and allow the “autorouter” to build the PCB for the DFT goals. The “Testpoint Manager” guides the user in sorting what could be up to thousands of test point pads or vias. After all points are set, the “Design Rule Checking” feature of Altium ensures that all test points adhere to the original set of Design Rules. Unfortunately, as of right now, Altium does not have a global manipulation of test points.
PCB traces and test points are one thing, but testing today’s SoCs or even dense and complex ICs is another. Building a circuit with test points around the chip is not the best way of identifying errors in the overall system; a SoC is an elaborate system of its own. Analysis has to go deeper.
Circuits today can be intimidatingly large. Fear of applying DFT practices at this scale is a mere aversion to the work. Automated testing like that found in Cadence’s Encounter products is a great start. Mixing it with good, old manual testing will give the best overall outcome.
Keep in mind, automated testing is not without its possible issues. DFT is a focus on testing at every point in the development stage. Collaboration between everyone in the chain of development is a good way to identify more areas that need attention for testing. Regardless of the results in testing options, manual or automatic, be thorough. Spend every dollar now in testing, or possibly lose every dollar of the profits.