Recently, our sister company UBM TechInsights presented a Webinar on how it uncovers the secrets within semiconductors and other bits of integrated circuitry used in the devices we’ve come to know and love.
For those not familiar with TechInsights, it’s the secret lab up in Canada where our colleagues rip open anything from cars such as the Chevy Volt to refrigerators, TVs, phones, tablets, laptops, smart meters, and more. Each dismembered product is carefully analyzed by TechInsights’ engineering teams, who get to do amazingly cool things, like dissolve devices in acid to figure out what materials they’re made of.
In fact, delayering semiconductor die is often useful for a plethora of applications -- circuit reverse engineering, failure analysis, transistor characteristics measurement, circuit edit, and more. Circuit extraction is likewise a good way to get valuable evidence of use in competing products that is difficult to find using other means -- so it’s a patent lawyer’s best friend.
TechInsights’ delayering techniques involve a wide range of parameters, which include effort, equipment, cost, risk, and accuracy -- so choosing the right process, tools, and techniques is vital. It also, of course, requires sound knowledge of semiconductor architecture to sketch circuit design schematics for our readers.
Indeed, TechInsights CircuitVision goes a step further and offers a highly interactive, easy-to-navigate view into circuit designs, as well as the physical implementation on the IC. Hierarchical schematics demonstrate the design from the block down to gate level -- all linked to the original layout, showing the extracted gates and associated interconnect.
Trust me, it’s neat. And not only is it neat, but for the first time ever, TechInsights is baring all with a Webinar of the delayering process, as well as the tools and expertise it uses to discover how a processor was designed, formulated, and built -- after it was actually delivered to market.
You can see the free presentation here (just fill out the short form prior to downloading). Warning: this presentation has a heavy geek factor!
What are they afraid of, indeed. There is plenty to be cautious of, and screening email domains is only about as effective as skeleton key lock.
More specifically, I am surprised that the detailed process of reverse engineering is being openly shared at all.
Initially, engineering details and processes ought to be closely guarded. Industrial intelligence is a big issue, and as the article states, its familiar territory to patent attorneys regarding infringement and detection.
Contrary and oppositional to that is the reverse engineering process. In this article, examples of very sophisticated methods and procedures used to discover that which often remains undetected, unless very advanced methods are used to determine such specific design intents.
Those very methods of determination ought to circle back 180° to the initial point; these are engineering secrets in and of themselves that ought to remain closely guarded.
UBM's decision to openly share their discoveries is a step towards a very open-source society of design engineers, but I can only imagine the angst it brings to those companies whose secrets are being publicized.
I have a paid gmail account. They use this as an excuse to prevent false registrants.
How silly this makes them look!!
Anyone can go to go-daddy, pay $10 for a .com domain with 5 free email accounts and fool the system. Any serious industrial spy would easily penetrate your security.
What it does do is block the large number of people who have various free or low cost accounts for no good reason. It also reveals they seem to spy on you.
Just an FYI, I went to download the webinar and it didn't like my email address - I got this message:
Please input a valid email address from a non-free provider.
My provider is "non-free" in that I do pay for it - it's not a yahoo or hotmail account, so I am puzzled as to why it doesn't like it or even why it makes a distinction...so unfortunately I can't access the webinar.
That said - fascinating topic! I remember in my product engineering days at Dallas Semiconductor - back in 1990 I got to participate in some failure analysis at the chip level. If I recall correctly, we used an electron microscope and we isolated some transistors on a chip by zapping lines with lasers - very fun stuff! There is something fascinating about working at that level - I usually worked with discretes but once in a while we would work with a wafer or chip. I remember picking up a wafer with the suction tool. I was fine until my boss commented that I was holding about ten thousand dollars in my hand!
In the old days failure analysis procedures were less formal. i remember an old FA guy showing me how to get to the chip on a ram I needed to open up and look at. It looked like a mad scientist laboratory with a beaker of acid smoking under the vent-a-hood. He had a fixture to use with the acid and the idea was to hold it to the top of the part until it ate away enough to expose the chip. I asked him how he knew it was time to remove the fixture and his reply was - until its too hot for you to hold any more!
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