The companies most directly involved in multicore processors, notably Intel, also are concerned with improving gate performance without make the chip interconnects too small to be reliable. Consequently, they have turned to gates (the active transistor element) that are themselves implemented in three dimensions, like Intel's Tri-Gate. Combine that with 3D packages, and suddenly a multicore chip can drive multiple communication interfaces at once.
Now, let's look at the efforts to drive individual communication channels to speeds of 100Gbits, and eventually a terabit, per second. A few years ago, system vendors turned from parallel to serial communications, because parallel buses were just too hard to work with. But behind the scenes, chip vendors reintroduced some parallel techniques inside the chips, all in an effort to shrink size and power. If you take a careful look at the 40Gbit ports planned for future Ethernet systems, you'll see four channels of 10Gbit interfaces at the edge of a chip. For 100Gbit ports, you'll see either 10 channels of 10Gbit serial interfaces or four channels of 25Gbit ones.
Firms like Vitesse Semiconductor and Applied Micro, which make the physical interfaces in question, were the first to push the channelization of interfaces. Luckily, they got a lot of support from the people who make the fiber-optic components that link communication chips to long-haul fibers.
When a coalition called the Optical Internetworking Forum got started 10 years ago, it dealt with fiber-optic algorithms and could barely speak chip talk. In the last couple of years, the OIF has become the semiconductor maker's best friend by promoting standards for optical modules that help define and drive a high-speed channelized interface -- standards like the Common Electrical Interface.
Ten years ago, there were dozens of router, switch, and optical transport system companies that cared about such chip-level and fiber-level interfaces. But the double whammy of the 2001 Internet crash and the 2008 global financial crash reduced the list of system players in telecommunications equipment to Cisco, Alcatel-Lucent, Ericsson, Huawei, ZTE, and very few others.
So why is this important? Well, the universal acceptance of IP and Ethernet means all new base stations for wireless networks use elements of these standards, as well. So do the storage area networks that once relied on Fibre Channel, and so do supercomputer clusters. In fact, the universe of players that can take advantage of small, power-efficient communication chips might be almost as large as the vast array of consumer devices out there -- or at least as diverse a user base.
One of the reasons that temperature and power dissipation have become such large issues is that increased speed has increased the number of operations per second, while the power dissipation per operation has not dropped that much. The reason for the speed increase can be partly shown to be inefficient software, more commonly called "bloatware". Of course it is easier and faster to write, but poorly written code wastes power. The excuse for allowing code that is not efficient has been that memory and processing power were so cheap that they could make up for the poor code. Now it is becoming clear that this is a bad choice, since the devices have become so very small, leading to much higher power densities.
One means of reducing the heat load, then, would be to use better code, and slow down the processor a bit. Of course this will require a level of programming skill that is not very common, and also a reduction in the number of useles features that seem to be everywhere. But it is the one solution that does not wind up challenging the basic laws of physics.
Airborne is the first sector we'll see, with mini-drones already requiring DSP capability in a vastly shrunken space. Automotive is always a field ripe for more dashboard integration, but I'd expect medical electronics to increase demands fairly quickly. Medical record digitization has accelerated now that hospitals are accepting tablets as a better alternative than laptops, and this will drive an overall move to get patient data acquisition into handheld platforms whenever and wherever possible.
What's your sense of the thermal and packaging challenge in the embedded space as MCU vendors pack more and faster cores (dual core) into what used to be fairly standardized and not all that cutting edge parts?
Gigabit and PoE are two networking technologies moving ahead in tandem as industrial users power remote Ethernet devices such as IP security cameras at 1,000 Mbps over existing CAT5 cable.
New disc magnet motors fit into the design trend of stepping up to closed loop performance while maintaining the cost advantage of stepper motor technology.
At the Design News webinar on June 27, learn all about aluminum extrusion: designing the right shape so it costs the least, is simplest to manufacture, and best fits the application's structural requirements.
A new battery design, which replaces lithium with abundant and low-cost elemental sulfur, is still in its nascent stages but shows real promise for giving batteries more energy potential.
From Dell / Intel® New Paradigms in Design Work Scott Hamilton, vertical market strategist for Dell Precision workstations, 5/2/2013 5
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