Thanks to the advent of dual-plane processors in routers and switches, and the use of multiple ARM or MIPS cores in single-chip wireless designs, multicore devices now are offered at prices cheap enough for many embedded applications in automotive, medical, industrial, and military-aerospace applications. But before designers begin a stampede to force-fit an Intel i7 into a process-control monitor where it doesn't belong, developers need to think long and hard about what the multicore attribute means in this environment.
Embedded applications have space, power, and cost constraints that place two distinct types of restrictions on multicore architectures. On the hardware front, highly specific processor tasks may mean that throwing a traditional symmetric multiprocessing (SMP) architecture at a problem may not give the designer the ultimate bang for the buck.
The solution may not be quad-way, eight-way, or 16-way ARM, but, rather, a mix of control-plane, datapath, and offline processors that play different roles inside one chip -- the so-called asymmetric multicore designs
offered by many vendors such as Cavium Networks, NetLogic Microsystems, and several FPGA specialists.
On the software front, developers need to examine how best to partition required tasks across multiple processors in a chip. When the division of labor in a microprocessor is symmetrical, software developers merely need to look at efficient multi-threading, task management, instruction parallelization, and task virtualization. But when a single chip is parceled into asymmetric modules, software also must manage such tasks as on-chip communication control, in-stream packet processing, inline and offline encryption, and look-aside specialized tasks such as TCP offloads.
In short, it is very easy for a multicore device designed for embedded efficiency to require more complex software, and offer greater hardware specialization, than a multicore device designed for the IT world. Given the tighter cost constraints in many embedded vertical markets, this demands a close look at how embedded processors move to multicore feature sets.
In the client-server world, more cores on a chip means greater processing performance for a specified series of tasks. Certainly, the virtualization of a single processor into multiple task kernels has led to greater complexity for the chips that serve this world, but software developers could look to the SIMD (single-instruction/multiple-date) and MIMD (multiple-instruction/multiple-date) programming models developed in the high-performance computing world as a guide to planning server performance with multicore chips. Only recently have such chips broken the barrier of eight-way processing to offer decent performance gains with 16, 32, or more cores.