ELECTRONICS: The Avnet Electronics Marketing operating group of Avnet Inc. introduced the Xilinx®Spartan®-6 FPGA DSP Development Kit. Order entry is now open for the $1,995 kit, which includes a device-locked version of ISE® Design Suite: System Edition 11.4. Spartan-6 FPGAs produce up to 45 GMACs of performance in a single part, offering the ideal solution for cost-prohibitive designs.
The Spartan-6 FPGA DSP Development Kit enables users to focus on the unique value of their design with an easy entry point for using FPGAs for DSP. Aerospace and defense, wireless, ISM and other computationally-intensive applications demand digital signal processing performance and cost effective solutions.
The Spartan-6 FPGA DSP Development Kit combines a scalable development board, DSP IP, DSP Development tools, and a preconfigured and fully validated Spartan-6 DSP Targeted Reference Design. This design serves as a basis to illustrate DSP techniques and design flows for the Spartan-6 class of signal processing functions. The state of the art digital up converter (DUC) / digital down converter (DDC) Targeted Reference Design shows customers how to use advanced techniques such as clock over-sampling, time division multiplexing and signal processing and resource optimization with the high performance DSP48 slices. Both an RTL and Model-Based Design flows are included. The design flow, based on MATLAB® and Simulink® from the MathWorksTM, allows algorithm developers to create DSP hardware designs using a familiar modeling environment without the need to learn RTL. Experienced RTL designers are provided design techniques for creating efficient DSP hardware using ISE Design Suite and LogicCoreTM DSP IP along with verification methodologies for comparing functional correctness against high-level algorithm models.
Key deliverables of the Spartan-6 DSP Targeted Reference Design are:
Design source files for RTL and Simulink
Top level system integration RTL source files
Simulation environment
Testbenches
Implementation environment
Complete steps and parameters for design synthesis
MAP, place and route and timing closure
Targeted reference design tutorials including recommended flows for design modification and integration
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