Carl Duffy, Contributing Writer
I work for Freescale Semiconductor as an integrated circuit Test Engineer and recently came across an interesting problem. I started to see a lot of devices failing some digital tests and digging into it I noticed some signals were collapsing (see PIN_B and PIN_C in figure below). The signal on top, PIN_A, is an adjacent pin on the chip which is behaving appropriately. These are standard 3V CMOS digital outputs on a rather slow port with a period of about 38ns.
This situation occurred while testing a chip at wafer probe. We test every chip in its packaged form, but as a cost saving measure we also test each chip when it is still in wafer form to weed out defective devices before they go through the expensive packaging process. The noise or ringing you see on the signals is not atypical of the probecard environment where signals might travel through 50cm (20 inches) of cable or loadboard traces, pogo pins, and a 2cm unshielded probe needle. Bypass capacitors are far away from the chip.
As we debugged the problem we gathered a few clues. First, we noticed PIN_B and PIN_C were both powered by the same VDD and GND pads, however, PIN_A, gets its power from different VDD and GND pads. The problem comes on suddenly as VDD is increased. We also noticed that when the signals collapsed, the data coming out was still correct; only the voltages were wrong. The problem always happened when a certain data pattern was transmitted, but never happened when the part was retested later in its packaged form.
One of the early theories that we investigated was whether the collapse was caused by reflections on the signal lines. But reflections over this distance don’t take 3 microseconds. Reflections take only a few nanoseconds over these distances and are visible in the finer detail. (See figure below.)
We also ruled out programmable drive strength or slew rates, because the problem did not occur when testing packaged parts with the same program. They might exacerbate the problem by increasing the instantaneous demand for current and thus the voltage spikes, but they did not cause the problem. Clamping of the power supply also was not the culprit: If this were the problem we would have only seen the logic 1 voltage decrease. Logic 0 would have been stayed at 0V.
We ultimately isolated the problem: The supply to the output circuitry was turning off - but what was causing the signal to collapse? The source of this problem lies with the ESD (Electro Static Discharge) protection circuits that are present on all CMOS chips. ESD protection circuits reacted to excessive noise on the supplies presuming it to be an ESD event. To protect the CMOS gates the ESD circuitry turned on, providing a momentary short circuit for the charge. This had the effect of collapsing the output signals.
A specific data pattern on multiple pins caused the problem because multiple pins toggling simultaneously and quickly caused the worst case ringing conditions on the supply. It was worse at high voltage because that drew the most power and thus had the highest ringing. The data was still correct because the microprocessor’s core supply was separate from the supply on the pads, and it was the latter that was turning off.
So why did this only occur at probe? In this particular case, there was only one probe needle providing power to PIN_B and PIN_C but in the packaged part there were multiple bond wires providing power. This meant that at probe we were cramming all the current through one VDD pad. Factor in the inductance of the probe needles and the bypass capacitors being significantly further away, and you get increased ringing on the power supply which triggered the ESD circuitry. PIN_A had multiple power pads at probe so it did not have as much ringing.
Adequate bypass capacitors on VDD up close to a chip will counteract the inductance in the path between the board’s power supply and the power supply pad, but on a probe card it is impractical to place capacitors close to the chip. The logic values were still correct because the I/O (input/output) supplies do not control the data. The I/O circuits provide level shifting and isolate the power supply noise of pad circuitry from core logic circuitry. The problem was resolved on a second revision of the chip with the addition of extra power and ground pads for probe needles. You can see this in the significantly improved signal quality in the figure below.
While our design team had spent a lot of effort designing the package, running simulations and adding extra power pads to ensure that we did not have simultaneous switching noise on the outputs, they had not run those same simulations on the probe card environment where fewer power supply pads were present. The bottom line for the IC designer is that ATE test environments require extra consideration during the design process. The lesson for the circuit board designer is the importance of bypass capacitors and following the power recommendations of the IC supplier.
Carl Duffy is a Lead Test Engineer working on iMX multimedia products for Freescale Semiconductor in Austin, Texas.