How often have you heard about a low-power FPGA and thought that it was an oxymoron like jumbo shrimp? FPGAs use programmable fabric to create custom logic, but this flexibility comes at a cost -- usually around 10 times more silicon real estate and 10 times the power dissipation. Can we really claim any FPGA is low power? This topic came up in the chat session during my recent Design News Continuing Education Center course on energy harvesting for MCU and FPGA applications, and it seemed like a good topic to expand here.
Perhaps if we look at some marketing data (another oxymoron?), we can get a better idea of what low-power FPGAs really means. Let’s look at a low-power FPGA and compare common power metrics to a typical low-power MCU to try and better understand what a low-power FPGA really is.
Let’s start with the Lattice iCE40 LP FPGA family. This family of FPGAs offers from around 400 logic cells to almost 8,000. With a pin range from 30 to 180, you can craft some fairly powerful functions, and since on-chip non-volatile memory is used for configuration, it’s a single-chip solution that saves board space, cost, and power. On-chip dedicated inter-integrated circuits and serial-peripheral interface controllers provide efficient interfaces for the most common types of peripherals and make it easy to implement intelligent peripheral expanders that can offload high-power host processors. The 1,280-logic-cell iCE40 LP1K device has a static power specification of just 100 uA. Dynamic current can vary dramatically depending on the application -- just like in an MCU design -- but dynamic current of between 5 to 10 mA for medium-performance applications isn’t atypical.
Now higher performance and higher complexity FPGAs can burn much more static and dynamic power. For example, a Xilinx Spartan-6 device with 14,000 logic cells has a static current of close to 10 mA. You get around 10 times the capacity of the Lattice device, with 100 times the static current. Dynamic current scales similarly, so we can see that low-power devices can be a couple of orders of magnitude lower power than even their low-end FPGA cousins.
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How do these metrics compare to microcontrollers? Some of the newest MCUs offer very low standby power or even battery back-up modes with power in the nA range. Even mid-range devices can offer significant power savings at lower clock rates and in power-saving “power down” modes. For example, the NXP LPC112x MCU family uses only 220 nA in the deep power-down mode, 1.8 uA in the deep-sleep mode, and just a few mA in the active mode running at 50 MHz. These metrics are from 10 to 1,000 times better than those found in low-power FPGAs.
Now it’s also true that FPGAs can do lots of processing in a single clock cycle, and in an active mode this can deliver improvements on orders of magnitude over MCUs. So if power-efficient processing is what’s really needed, an FPGA just might be a better solution than an MCU. If low power is of primary importance, however, it looks like an MCU is the best approach -- at least for now.
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Thus it seems that low-power FPGAs are not as low power as our familiar MCUs, but they are lower power than other FPGAs. They definitely satisfy the demand for lower power required by battery-powered or energy-harvesting applications, where uA of static current and mA of operating current are key constraints. Perhaps these devices should really be marketed as lower-power FPGAs instead of low-power FPGAs. I guess if “jumbo shrimp” isn’t marketed as “jumbo-er shrimp,” we can’t really expect the FPGA marketers to do anything different.
Warren Miller has more than 30 years of experience in electronics and has held a variety of positions in engineering, applications, strategic marketing, and product planning with large electronics companies like Advanced Micro Devices, Actel, and Avnet, as well as with a variety of smaller startups. He has in-depth experience of programmable devices (PLDs, FPGAs, MCUs, and ASICs) in industrial, networking, and consumer applications and holds several device patents.
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