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Small-Scale Logic Packaging

New technologies shrink the footprint and weight of handheld products

Sujatha Garimella and Lance Wright, Contributing Writers -- Design News, August 14, 2006

The most advanced semiconductors provide incredible levels of integration. The 2006 forecast from the International Technology Roadmap for Semiconductors (ITRS) 2005 Edition indicates the transistor density for high-performance logic is 122 million transistors/cm2 with 193 million functions per chip and a chip size of 88 mm². At first glance, this high level of integration would seem to eliminate the need for logic products with just a few gates. However, last-minute changes and mistakes have continued to require these lower gate-count products, sometimes called "oops" logic.

In addition, growing consumer interest in portable electronics and handsets has challenged manufacturers to create new products that have a sophisticated exterior and an enhanced set of features. With PCBs becoming smaller and more complex, there is an increasing need for devices that are extremely small and simple. The reduced size allows small-scale logic packaging to create cost-effective designs and enable manufacturers to meet their time-to-market requirements. Products such as Little Logic, Texas Instruments' (TI's) term for Small-Scale Logic Packages (SSLPs), solve specific design problems with a very small form factor.

A Little Logic Goes a Long Way

A wide range of functions, from simple gates and translator functions to switches (analog and digital) and configurable devices, allows micro-miniature packages' usage in almost any application and serves four basic purposes, including: PCB space savings, simplified layout, ASIC bug-fixes and inventory control.

Saving PCB space is especially important in portable devices such as handsets that use miniaturized PCBs. One of the smaller packages, the NanoStar or Wafer Chip Scale Package (YZP) is 1.4 × 0.9 mm. Using a single-gate YZP (a die-size ball grid array) or dual-gate US8 package (DCU) offers from 35 to 96 percent space savings over a 14-pin TSSOP (Thin Shrink Small Outline Package).

SSLPs simplify PCB board layout by reducing or shortening the routing. This is a clear advantage over using multiple-gate devices requiring the routing of multiple etches from distinct partitions on a PCB through one logic device. The small package can be placed at the input and output of the microprocessor or at the input and output of an ASIC or anywhere in between.

Drawing on their oops-logic capability, these small logic packages provide an ASIC bug-fix option that maximizes design investment. If an ASIC output level error occurs, the designer would not need to redesign and manufacture the ASIC to modify the signal level. A single, dual- or triple-gate device can be used in several places to meet the specified voltage level and performance.

New configurable small-scale logic packaging devices (see sidebar) provide improved inventory control while saving valuable PCB space. In most cases, the choice to use these products is a last-minute decision for designers. While the SSLP is primarily used to fix "errors" in a system, designers are not aware of the logic functions needed until they encounter an application problem. To correct an error, a designer may need to build an inventory of several logic functions (such as inverters and gates) to determine which function is needed. This could be an issue for customers, as it increases time and cost required to manage inventory, and the use of multiple logic devices can occupy valuable PCB space. Configurable devices solve this problem with multiple functions in a single chip.

A Logical Choice for Small-Scale Logic Packaging

The handset market segment is extremely real estate constrained. The manufacturers focus on package solutions that maximize PCB space such as the Wafer Chip Scale Package (WCSP). Texas Instruments' NanoStar and NanoFree WCSP technology provide a specific solution for these applications.

WCSP has two advantages over lead-frame-based packages. First, these packages have better thermal performance than lead frame designs because of the BGA-style packaging. Second, WCSPs are 70 percent smaller than a 5/6-pin SC70 package and 72 percent smaller than an 8-pin US8. In addition to providing a two dimensional (length and width) space savings, the WCSP also provides volume savings since it is thinner than lead frame packages. Its extremely small size makes the WCSP highly useful for space-constrained PCBs.

Meeting a Small Challenge

Small-scale logic packaging and smaller die sizes are crucial for the industry's miniaturization trend in portable electronics. Furthermore, this design methodology provides faster time-to-market for all electronic products by using simplified designs and implementation. These diverse packages and functions are adaptable to almost any application.

Little Logic Package Comparison
Package	SOT-23	SC-70	SOT-553 SOT-563	SON	NanoStar		fSV
Pins	5,6	5,6	5,6	5,6	5,6		5,6
Description	Plastic SMT, leadframe-based, gull wing leads, die down, wire-bonded	Plastic SMT, leadframe-based, gull wing leads, die down, wire-bonded	Plastic SMT, leadframe-based, non-formed leads, die up, exposed pad optional, wire- bonded or Flipchip	Plastic SMT, leadframe, routed BT, or ceramic substrate, Land Grid Array, die up, wire-bonded or Flipchips	Direct bumped bare die SMT with repassivation, RDL (redistribution layer) optional		Plastic SMT, leadframe-based non-formed leads, die up, wire-bond or PC
Popular Uses (Single & Dual Gates)	Consumer Electronics	Consumer Electronics	Space constrained hand-held electronics	Space constrained hand-held electronics	Space constrained hand-held electronics		Space constrained hand-held electronics
Pitch (mm)	.95	.65	.50	.50	.50	40	.35
Length (mm)	2.90	2.00	1.60	1.45	1.40	1.20	1.00
Width (mm)	2.80	2.10	1.60	1.00	.90	.80	1.00
Area (mm²)	8.12	4.20	2.56	1.45	1.26	.96	1.00
Height (mm)	1.45	1.10	.55	.55	.50 or less		.50
Package Pluses	Easy to solder and handle, large pitch and large package size, large die size	Easy to solder and handle, large pitch size and large package size	Small package profile, low weight, easy to solder	Small package profile, low weight	Small package profile, large stand-off for improved BLR, best electrical parasitics, low pkg. weight, lower pkg. height, good workability	Small package profile, low weight, smallest pitch
Package Minuses	Package size too large for space-constrained applications	Package size too large for space-constrained applications	Limited to die size	Limited to die size, difficult to probe	Increased placement force sensitivity, difficult to probe		Small pitch can cause SMT difficulties. Need expensive stencils, limited die size
How to Overcome Minuses	Move to smaller package, die shrink, function change	Move to smaller package, die shrink, function change	Use Flipchip to get a larger die size and improve electrical parasitics, advanced silicon process to reduce die size	Use Flipchip to get a larger die size and improve electrical parasitics, use special probe tips or make land pad traces larger.	Good pick-and- place machine placement force setup, can use special probe tip or make land pad traces longer		Electro-formed and polished stencil

Join the conversation! For more detailed reviews from these readers and to add your comments, go to our Electronics Forum at: http://rbi.ims.ca/4930-538.

Configurable Logic

The term configurable logic is usually associated with large-scale integrated circuits, called programmable logic devices, with hundreds of macrocells and I/Os. The configurability is achieved by internally programmable interconnects. However, configurable logic is just as useful as a design methodology for small-scale ICs. In this case, the configurability comes from selecting the appropriate pinouts on the package. Examples of configurable Little Logic products are the SN74AUP1G97 and SN74AUP1G98. These devices offer nine single-gate logic solutions in one device. Besides the standard 2-input logic gate functions, the SN74AUP1G97 and SN74AUP1G98 both offer four additional functions previously requiring two ICs. Combining functions in this manner saves crucial board space.

A Logical Application for Small-Scale Logic Packaging

Handsets use Little Logic for the following functions:

The 1G80 function is often used as a clock divider. In this example, a 26 MHz clock signal from the digital baseband (processor) is divided in half for intermediate frequency filtering in the RF front end.
The 1G125 provides a clock buffer from the real-time clock chip to drive both the digital baseband and RF front end.
The 1G19 performs as a memory selector between the non-volatile memory (Flash) and volatile memory (SDRAM).
The 1G07 is an open-drain device used to level shift down a Card Detect signal from the MMC card.
The 1G04 and 1G97 implement control signals for starting/stopping infrared communication (hot sync contacts/calendar with PC, for example).
The 1G32 takes signals from the digital baseband and Bluetooth module to control a low drop-out regulator that powers the Bluetooth RF transmitter.
Finally, a 1G97 implements control signals for enabling/disabling the WLAN subsystem.

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Small-Scale Logic Packaging

New technologies shrink the footprint and weight of handheld products

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