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Hybrid 16-bit Controller Hits 60 MIPS
Core has CPU, DSP, and fast flash memory
Terry Costlow -- Design News, September 22, 2003
A 16-bit microcontroller from Motorola has DSP and flash memory, giving it enough performance to compete with low-end 32-bit chips. The 60 MIPS core is designed for automotive applications and motor/motion control.
The line retains the low cost of 16-bit chips with base versions priced at under $10 in quantity purchases. The 56F8300 family also claims a number of tools that should simplify programming.
The high-speed, low-cost system-on-a-chip core is designed to hit a level between the power of today's 16-bit ICs and more costly 32-bit architectures. "If a chip with 10-30 MIPS won't do the job, this will take you up to 60 MIPS," says Scott Lynch, Operations Manager at Motorola's DSP Operation (www.motorola.com/mcu) in Tempe, AZ.
The line offers from 32 to 256 Kbytes of flash memory, providing fast access to data. "The line runs at a sustained rate of 60 MIPS from flash. It's the fastest flash on the market," Lynch says.
One of the key target markets is the booming automotive industry, where the number of microcontrollers is growing substantially. The typical car currently has around 20 microcontrollers, while high-end vehicles are closing in on 100.
"Half our business will be in automotive," Lynch says. He adds that in automotive, as in other applications, "flash is an enabler." The peripherals that can be added to the core processor include a pair of CAN bus interfaces, addressing the trend to link control units together.
An operating temperature of -40 to 125C meets the extreme environmental demands in the automotive field. Operating temperatures are a big factor for flash circuitry, so parts going into autos often have less flash memory than chips going into less severe consumer products, Lynch adds. The flash also has security features so code can't be stolen.
The core has enough processing capability to do some tasks without requiring external sensors, which can reduce cost and simplify production. In a seat motor or other positioner, the chips can count the rotation of a shaft and monitor its position, eliminating sensors often used to determine position.
The device has a number of additional peripherals developed for use in motor and motion control applications. It has a pair of six-output PWM cores, as well as a quad time module and two quadrature decoders.
Safety features include an automatic shutdown in the PWM functions, so that if sensors show problems with a motor, it will be shut down without delays that can occur with some chips if they have software interruptions. An on-chip temperature sensor also permits graceful shutdown if the die gets too hot. Write protection registers also help during unexpected shutdowns.
Functions of the Harvard architecture DSP include a multiplier accumulator with single and dual parallel move instructions, no overhead hardware looping, and nested interrupt with hardware priority.
The line is designed to let engineers move freely up and down the performance level, using similar software for all versions. Code is compatible with the first generation 56800 architecture. It uses Code Warrior, which also works with Motorola's HCS12 and HC08 processor lines. Processor Expert, an auto code generator, will help speed development time while giving engineers the freedom to upgrade products and use the same code for different performance levels throughout their product lines.
"Once designers are familiar with Code Warrior and Processor Expert, they can easily develop and move code from one member of the line to another," Lynch says. There are currently six members in the line, with nine more coming next year.
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