RSS Feeds
FPGAs Advance to Meet Communications Speeds
As field-programmable gate arrays (FPGAs) evolve, their built-in circuitry enables communications in the multi-gigabit range
Alan Earls, Contributing Editor -- Design News, October 30, 2008
A confluence of technological advancements has propelled
FPGAs forward presenting
systems designers with attractive solutions that deliver higher performance in
smaller spaces. With the advent of system on a chip (SOC) technology, several
disparate functions have been condensed and now reside on a single chip. These
complex devices now have such functions as Ethernet MACs (media access
controllers), embedded processors, DSP blocks and high speed I/O embedded in
their architectures.
In addition, several serial standards and protocols such as PCI Express, Serial Rapid I/O, Ethernet, Fibre Channel and SerialLite have enabled widespread acceptance of high-speed serial transceivers embedded into today's system on a chip FPGAs. Now it is not uncommon to find 3.125-Gbits/s or even 6.5 Gbits/s high-speed transceivers on an FPGA. However, with multiple functions and high-speed communications capability on board, FPGAs still need to interface with other components to realize their true potential.
Fortunately, the evolution of SOC technology and circuit board assembly technology have occurred on parallel paths. In fact, ease of integration represents one primary driver behind FPGA proliferation. Unlike the recent past, when system developers grappled with integration issues presented by multiple chip solutions, these new FPGAs with embedded functionality offer near plug and play capability - using standard surface mount technology processes for mounting on boards - since the integration has already taken place inside the chip.
That integration can be enhanced in some devices by replacing metal interconnect layers with vertical connections inside the chip to solder bump arrays that protrude through the chip package for eventual alignment with board pads during the surface mount soldering process. Not only does this ease integration with board assembly, it also further optimizes signal integrity and facilitates speed by providing the shortest path possible for signal travel.
The 65nm Virtex®-5 family from Xilinx delivers the newest and most powerful features available on the market today. The Virtex-5 family is made up of five distinct platforms optimized for logic functions, high-speed serial I/O, DSP and embedded processing. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIOTM technology with built-in digitally controlled impedance, ChipSyncTM source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (digital clock managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options.
Additional platform dependent features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI ExpressTM compliant integrated Endpoint blocks, tri-mode Ethernet MACs, and high-performance PowerPC® 440 microprocessor embedded blocks.
"These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems," says Brent Przybus, Senior Marketing Manager for advanced products at Xilinx. "Virtex-5 FPGAs deliver a risk-free alternative to custom ASICs because they offer a broad range of advanced, domain-optimized system-on-chip features and are supported by industry-leading tools, IP, and technical services."
Clearly, FPGA technology is poised for proliferation across multiple applications and industries. The benefits of smaller footprint, lower power consumption, increased flexibility and performance, faster speeds, affordable cost, and the absence of interfacing issues with two-chip solutions make FPGA SOCs with the embedded accoutrements described above an elegant solution for board designers. Moreover, as these advanced devices gain critical mass, we will certainly see them designed in to more and more applications.
