DAY5: CORTEX-M0 in Commercial Components, Summer 2012
Continuing Education Center 8/24/2012 364 comments This discussion presents an overview of commercial CORTEX-M0 components. We present component families from Freescale, Nuvoton, NXP, and ST Microelectronics. This discussion provides insight into today’s available product. Our objective is to provide information about today’s commercial devices and how a designer might select a particular part.
DAY4: CORTEX-M0 Structure, Discussion 3
Continuing Education Center 8/23/2012 267 comments This discussion is the third of three views into the details of the CORTEX-M0 processor features. Presented from the point of view of an embedded system designer, this discussion will address four of the key features of the CORTEX-M0 processor, which provide the competitive advantage the M0 is famous for. Those areas are power management, exception handling, stack structures, and SVC/WFE/WFI instructions.
DAY3: CORTEX-M0 Structure, Discussion 2
Continuing Education Center 8/22/2012 275 comments This discussion is the second of three views into the details of the CORTEX-M0 processor features. Presented from the point of view of an embedded system designer, this discussion will address the following features of the CORTEX-M0 processor: the SYSTICK core peripheral, the NVIC core peripheral, the SCB core peripheral, and the MPC core peripheral.
DAY2: CORTEX-M0 Structure, Discussion 1
Continuing Education Center 8/21/2012 244 comments This discussion is the first of three views into the details of the CORTEX-M0 processor features. Presented from the point of view of an embedded system designer, this discussion will address four different aspects of the CORTEX-M0 processor. They include the instruction set, the memory map, the register set, and the execution modes.
DAY 1: The 8 / 32 Bit Difference, an Overview
Continuing Education Center 8/20/2012 349 comments This discussion shows by example the advantages of the CORTEX-M0 architecture over older 8- or 16-bit small computer embedded architectures. Performance and code style advantages will be discussed. On-chip peripheral features of older devices will be contrasted with those of today’s modern devices. Our objective is to provide a well rounded understanding of the new 32-bit CORTEX-M0 landscape.
Part V: Compiling Your Kernel
Continuing Education Center 8/10/2012 496 comments The fifth and final course for the week will start with a demonstration on compiling the kernel with debugging information enabled. It then will delve in the KDB symbolic debugger/disassembler and KGDB source debugger. Before doing a wrap-up, Anderson will show how to employ hardware debuggers such as JTAGs.
Part IV: The Nitty Gritty of Debugging
Continuing Education Center 8/9/2012 353 comments Getting down to the fine art of debugging, Anderson will go into detail on three operations: Ftrace, Oprofile, and LTTng. What these techniques mean and how they are applied will be the crux of this lesson.
Part III: The Ins & Outs of DebugFS
Continuing Education Center 8/8/2012 417 comments The third class lets the students virtually roll up their sleeves and begin enabling and using DebugFS. They'll also learn how to use kprobes, jprobes, and jretprobes. Finally, the SystemTap will be explained in detail.
Intro: Introduction to Linux Debugging
Continuing Education Center 8/6/2012 515 comments During the first class, students will learn how to get code into the kernel with kernel loadable modules. They'll learn how problems manifest themselves in the kernel, specifically referring to kernel panics, kernel oops, and other improper behaviors. After analyzing panics/oops to find the next step, the class will wrap up by watching interactions between user-space and kernel space via strace.
The engineers and inventors of the post WWII period turned their attention to advancements in electronics, communication, and entertainment. Breakthrough inventions range from LEGOs and computer gaming to the integrated circuit and Ethernet -- a range of advancements that have little in common except they changed our lives.
The age of touch could soon come to an end. From smartphones and smartwatches, to home devices, to in-car infotainment systems, touch is no longer the primary user interface. Technology market leaders are driving a migration from touch to voice as a user interface.
Soft starter technology has become a way to mitigate startup stressors by moderating a motor’s voltage supply during the machine start-up phase, slowly ramping it up and effectively adjusting the machine’s load behavior to protect mechanical components.
A new report from the National Institute of Standards and Technology (NIST) makes a start on developing control schemes, process measurements, and modeling and simulation methods for powder bed fusion additive manufacturing.
If you’re developing a product with lots of sensors and no access to the power grid, then you’ll want to take note of a Design News Continuing Education Center class, “Designing Low Power Systems Using Battery and Energy Harvesting Energy Sources."
Focus on Fundamentals consists of 45-minute on-line classes that cover a host of technologies. You learn without leaving the comfort of your desk. All classes are taught by subject-matter experts and all are archived. So if you can't attend live, attend at your convenience.