DAY5: CORTEX-M0 in Commercial Components, Summer 2012
Continuing Education Center 8/24/2012 364 comments This discussion presents an overview of commercial CORTEX-M0 components. We present component families from Freescale, Nuvoton, NXP, and ST Microelectronics. This discussion provides insight into todayís available product. Our objective is to provide information about todayís commercial devices and how a designer might select a particular part.
DAY4: CORTEX-M0 Structure, Discussion 3
Continuing Education Center 8/23/2012 267 comments This discussion is the third of three views into the details of the CORTEX-M0 processor features. Presented from the point of view of an embedded system designer, this discussion will address four of the key features of the CORTEX-M0 processor, which provide the competitive advantage the M0 is famous for. Those areas are power management, exception handling, stack structures, and SVC/WFE/WFI instructions.
DAY3: CORTEX-M0 Structure, Discussion 2
Continuing Education Center 8/22/2012 275 comments This discussion is the second of three views into the details of the CORTEX-M0 processor features. Presented from the point of view of an embedded system designer, this discussion will address the following features of the CORTEX-M0 processor: the SYSTICK core peripheral, the NVIC core peripheral, the SCB core peripheral, and the MPC core peripheral.
DAY2: CORTEX-M0 Structure, Discussion 1
Continuing Education Center 8/21/2012 244 comments This discussion is the first of three views into the details of the CORTEX-M0 processor features. Presented from the point of view of an embedded system designer, this discussion will address four different aspects of the CORTEX-M0 processor. They include the instruction set, the memory map, the register set, and the execution modes.
DAY 1: The 8 / 32 Bit Difference, an Overview
Continuing Education Center 8/20/2012 349 comments This discussion shows by example the advantages of the CORTEX-M0 architecture over older 8- or 16-bit small computer embedded architectures. Performance and code style advantages will be discussed. On-chip peripheral features of older devices will be contrasted with those of todayís modern devices. Our objective is to provide a well rounded understanding of the new 32-bit CORTEX-M0 landscape.
Part V: Compiling Your Kernel
Continuing Education Center 8/10/2012 496 comments The fifth and final course for the week will start with a demonstration on compiling the kernel with debugging information enabled. It then will delve in the KDB symbolic debugger/disassembler and KGDB source debugger. Before doing a wrap-up, Anderson will show how to employ hardware debuggers such as JTAGs.
Part IV: The Nitty Gritty of Debugging
Continuing Education Center 8/9/2012 353 comments Getting down to the fine art of debugging, Anderson will go into detail on three operations: Ftrace, Oprofile, and LTTng. What these techniques mean and how they are applied will be the crux of this lesson.
Part III: The Ins & Outs of DebugFS
Continuing Education Center 8/8/2012 417 comments The third class lets the students virtually roll up their sleeves and begin enabling and using DebugFS. They'll also learn how to use kprobes, jprobes, and jretprobes. Finally, the SystemTap will be explained in detail.
Intro: Introduction to Linux Debugging
Continuing Education Center 8/6/2012 515 comments During the first class, students will learn how to get code into the kernel with kernel loadable modules. They'll learn how problems manifest themselves in the kernel, specifically referring to kernel panics, kernel oops, and other improper behaviors. After analyzing panics/oops to find the next step, the class will wrap up by watching interactions between user-space and kernel space via strace.
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